JPS62229965A - Multilayered insulating film - Google Patents
Multilayered insulating filmInfo
- Publication number
- JPS62229965A JPS62229965A JP7124586A JP7124586A JPS62229965A JP S62229965 A JPS62229965 A JP S62229965A JP 7124586 A JP7124586 A JP 7124586A JP 7124586 A JP7124586 A JP 7124586A JP S62229965 A JPS62229965 A JP S62229965A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- insulating films
- capacitor
- forbidden band
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 6
- 230000006866 deterioration Effects 0.000 abstract description 6
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 abstract description 6
- 230000001590 oxidative effect Effects 0.000 abstract description 5
- 238000005381 potential energy Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 34
- 230000015556 catabolic process Effects 0.000 description 13
- 239000010410 layer Substances 0.000 description 12
- 230000007774 longterm Effects 0.000 description 12
- 230000005684 electric field Effects 0.000 description 11
- 230000007547 defect Effects 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000009413 insulation Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層絶縁膜に係り、特に大規模集積回路（ＬＳ
Ｉ）用キャパシタ用絶縁膜に適用するのに好適な多層絶
縁膜に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a multilayer insulating film, particularly for large-scale integrated circuits (LS
The present invention relates to a multilayer insulating film suitable for application to an insulating film for a capacitor for I).
ダイナミックメモリや高速バイポーラメモリＬＳＩの高
集積化が進められているが、高集積化を達成するために
は、特開昭５３−１０８３９２号公報に記載しであるよ
うに、キャパシタの面積を縮少することが不可欠である
。所定の容量のキャパシタの面積を縮小する場合、同一
の容量を得るためにはキャパシタ用絶縁膜の膜厚を薄く
しなければならない、しかし、従来、キャパシタ用絶縁
膜として用いられてきたＳｉｎ、膜の薄膜化には限界が
あるので、特開昭５６−１３５９３６号公報において不
揮発性メモリ用絶縁膜として提案されている５ｉＯｚ／
Ｓ ｉ３Ｎ ４ ／ ｓ ｉ ｏ 、構造の多層膜をキ
ャパシタ用絶縁膜として用いることが提案されている（
インターナショナル リライアビリティ フィジックス
シンポジウム、プレゼンテーション アブストラクト（
ＩＮＴＥＲＮＡＴＩＯＮＡＬ Ｒ１１！ＬＩＡＢＩＬＩ
ＴＹ Ｐ）ＩＹＳＩＣ５ＳＹＭ−ＰＯＳＩＵＭ、ＰＲＥ
ＳＥＮＴＡＳＩＯＮ ＡＢＳＴＲＡＣＴ） １９８５年
３月２５日〜２９日第１．４〜１頁）、シかし、このよ
うな多層絶縁膜構造がキャパシタ用絶縁膜として最適で
あるかどうかについては考慮されていなかった。High integration of dynamic memory and high-speed bipolar memory LSI is progressing, but in order to achieve high integration, it is necessary to reduce the area of the capacitor, as described in Japanese Patent Application Laid-open No. 108392/1983. It is essential to do so. When reducing the area of a capacitor with a given capacity, the thickness of the capacitor insulating film must be reduced in order to obtain the same capacity.However, the thickness of the capacitor insulating film must be reduced. Since there is a limit to the thinning of the film, 5iOz/
It has been proposed to use a multilayer film with a Si3N4/sio structure as an insulating film for a capacitor (
International Reliability Physics Symposium, Presentation Abstracts (
INTERNATIONAL R11! LIABILI
TYP) IYSIC5SYM-POSIUM, PRE
SENTASION ABSTRACT) March 25-29, 1985, pages 1.4-1), however, no consideration was given as to whether such a multilayer insulating film structure was optimal as an insulating film for capacitors. .
上記従来技術のＳ １０２ ／ Ｓ １ ｚ Ｎ ４
／ Ｓ ｎｏ ２構造の３層絶縁膜は、これまでＳｉｎ
、の単層膜と比較して欠陥密度が少ないことから検討さ
れてきた。S 102 / S 1 z N 4 of the above conventional technology
/ The three-layer insulating film with S no 2 structure has been
has been studied because of its lower defect density compared to single-layer films.
すなわち、ＳｉＯ□単層膜においては、膜厚の薄膜化と
ともに、ピンホールが発生してキャパシタの短絡（ショ
ート）の原因となる。Ｓｉｏ２／Ｓ ｉ、 Ｎ、／ Ｓ
ｉｏ、構造の３層絶縁膜の場合を第４図を用いて説明
する。That is, in the SiO□ single-layer film, as the film thickness becomes thinner, pinholes are generated, which causes a short circuit in the capacitor. Sio2/S i, N, /S
The case of a three-layer insulating film having a structure of .io and .io will be explained with reference to FIG.
第４図は、このような構造の従来の多層絶縁膜を誘電体
として用いたＭＯＳキャパシタの断面図である。第４図
において、１はＳＬ基板、６．８は５ｉｎ２膜、７はＳ
ｉ、Ｎ、膜、９は多結晶Ｓｉ電極を示す。キャパシタは
、多結晶ＳＬ電極９とＳｉ基板１の間に形成される。FIG. 4 is a cross-sectional view of a MOS capacitor using a conventional multilayer insulating film having such a structure as a dielectric. In Figure 4, 1 is the SL substrate, 6.8 is the 5in2 film, and 7 is the S
i, N, film, 9 indicates a polycrystalline Si electrode. A capacitor is formed between polycrystalline SL electrode 9 and Si substrate 1.
まず、Ｓｉ基板１上にＳ ｉｏ、膜６を熱酸化法により
形成し、その上に５Ｌ３Ｎ、膜７をＣＶＤ法により積層
し、その上にＳｉ、Ｎ４膜７の表面を酸化してＳｉｏ２
膜８を形成する。その後、Ｓｉｎ、［８の上にＳ ｉｏ
２膜８の上に多結晶Ｓｉ電極９を形成した。First, an Sio film 6 is formed on a Si substrate 1 by a thermal oxidation method, a 5L3N film 7 is laminated thereon by a CVD method, and the surface of the Si, N4 film 7 is oxidized to form an Sio2
A film 8 is formed. Then Sin, [S io on top of 8
A polycrystalline Si electrode 9 was formed on the second film 8.
本実施例の３層絶縁膜では、各絶縁膜（６，７，８）に
ピンホールが存在しても、積層することによって、ピン
ホール部分が原因となるキャパシタの短絡を防止できる
。ところが、上記多層絶縁膜は長時間の電圧印加による
ストレスによって耐圧の劣化が生じ、充分な信頼度が確
保しにくいことがわかった。In the three-layer insulating film of this embodiment, even if a pinhole exists in each insulating film (6, 7, 8), by stacking the films, it is possible to prevent a short circuit in the capacitor caused by the pinhole portion. However, it has been found that the withstand voltage of the multilayer insulating film deteriorates due to stress caused by long-term voltage application, making it difficult to ensure sufficient reliability.
本発明の目的は、欠陥密度が少なく、かつ、長時間の電
圧ストレスによっても耐圧の劣化の生じない多層絶縁膜
を提供することにある。An object of the present invention is to provide a multilayer insulating film which has a low defect density and whose breakdown voltage does not deteriorate even under long-term voltage stress.
上記目的を達成するために、第４図に示した３層絶縁膜
（Ｓｉｎ、／ ＳＬ、Ｎ、／ ５ｉｎ２） （１）耐圧
劣化の原因を検討した。第２図は、第４図の３層絶縁膜
のエネルギーバンドの模式図である。外側の絶縁■愼で
あるＳｉｏ、膜６．８の禁制帯のエネルギー幅（バンド
ギャップ）は約８ｅＶであり、内部の絶縁膜であるＳＬ
、Ｎ、膜７の禁制帯のエネルギー幅約５ｅＶより大きい
ので、Ｓｉ基板１から注入された電子ｅ−はＳｉＯ□膜
６のエネルギー障壁を乗り越えた後、５１３Ｎ４膜７中
でエネルギーを失い、例えば、Ｓｉｎ、膜８とＳＬ、Ｎ
４膜７の界面の位置エネルギーの谷間に電荷Ｑ工が蓄積
される。In order to achieve the above objective, we investigated the causes of the three-layer insulating film (Sin, /SL, N, /5in2) shown in FIG. 4 (1) breakdown voltage deterioration. FIG. 2 is a schematic diagram of the energy band of the three-layer insulating film shown in FIG. 4. The energy width (bandgap) of the forbidden band of the outer insulating film Sio and film 6.8 is approximately 8 eV, and the inner insulating film SL
, N, the energy width of the forbidden band of the film 7 is larger than about 5 eV, so the electrons e- injected from the Si substrate 1 lose energy in the 513N4 film 7 after overcoming the energy barrier of the SiO□ film 6, and e.g. , Sin, film 8 and SL, N
Charges Q are accumulated in the valley of potential energy at the interface of the four films 7.
この結果、ｓｉｏ、ｖ４ｇに強い内部電界が発生し、Ｓ
ｉｏ、膜８が絶縁破壊を起こす。この後、残ったＳｉ、
Ｎ４膜７、Ｓｉｏ、膜６に高電界が印加サレ、リーク電
流が増加して、誘電体全体の破壊に至る。As a result, a strong internal electric field is generated in sio, v4g, and S
io, the membrane 8 undergoes dielectric breakdown. After this, the remaining Si,
A high electric field is applied to the N4 film 7, Sio film 6, and the leakage current increases, leading to destruction of the entire dielectric.
上記のモデルでは電子ｅ−の注入による場合を示したが
、Ｓｉ基板１の導電型またはキャリアの種類によって、
ホールの注入が起こる。この場合には、電極９からホー
ルｈ＋が注入され、ＳｉＯ□膜６と５１３Ｎ４膜７の界
面の位置エネルギーの谷間にホールｈ＋が蓄積してＱ２
の電荷量となる。The above model shows the case where electrons e- are injected, but depending on the conductivity type of the Si substrate 1 or the type of carrier,
Hole injection occurs. In this case, holes h+ are injected from the electrode 9, and accumulate in the potential energy valley at the interface between the SiO□ film 6 and the 513N4 film 7, resulting in Q2
The amount of charge is .
この結果、Ｓｉｎ、膜６に強い内部電界が発生し。As a result, a strong internal electric field is generated in the Sin film 6.
まずＳｉｏ２膜６が絶縁破壊を起こす。この後、残った
５１３Ｎ４膜７、Ｓｉｏ、膜８に高電界が印加され、リ
ーク電流の増加が起こり、誘電体全体の破壊に至る。な
お、この従来構造においては、電荷Ｑ１、Ｑ２は、スト
レス電圧が除かれた後でも、Ｓｉ、Ｎ４膜７中もしくは
５１３Ｎ４膜７とＳｉｏ２膜６゜８の界面に残存する。First, dielectric breakdown occurs in the Sio2 film 6. After this, a high electric field is applied to the remaining 513N4 film 7, Sio, and film 8, causing an increase in leakage current, leading to destruction of the entire dielectric. In this conventional structure, the charges Q1 and Q2 remain in the Si, N4 film 7 or at the interface between the 513N4 film 7 and the Sio2 film 6.8 even after the stress voltage is removed.
本発明の多層絶縁膜は、このような検討結果から見い出
され、複数の絶縁膜を重ねることにより、短絡の原因と
なるピンホールを減少させ、欠陥密度を減らすと共に、
内部の絶縁膜の禁制帯のエネルギー幅を外側の絶縁膜の
禁制帯のエネルギー幅よりも大きくすることにより、耐
圧劣化の原因となる位置エネルギーの谷間を形成しない
で、長期信頼性のあるキャパシタ用誘電体を提供するも
のである。The multilayer insulating film of the present invention was discovered from the results of these studies, and by stacking multiple insulating films, it reduces pinholes that cause short circuits, reduces defect density, and
By making the energy width of the forbidden band of the inner insulating film larger than the energy width of the forbidden band of the outer insulating film, we have created a capacitor with long-term reliability without forming potential energy valleys that cause breakdown voltage deterioration. It provides a dielectric material.
本発明の多層絶縁膜においては、上述のように、内部の
絶縁膜の禁制帯のエネルギー幅が外側の絶縁膜の禁制帯
のエネルギー幅より大きいので、従来の多層絶縁膜が有
する位置エネルギーの谷間（第２図）が存在せず、絶縁
膜に注入されたキャリアの電子ｅ−またはホールｈ＋が
絶縁膜を容易に通過することができ、絶縁膜界面での電
荷の蓄積を起こりにくくできる。また、仮りに電荷の蓄
積が起こっても、この電荷は絶縁膜に印加される電圧の
変動によって容易に絶縁膜の外に掃き出されるため、絶
縁膜中に電荷が蓄積されにくい、従って、電荷の蓄積に
伴う内部電界の増大により。In the multilayer insulating film of the present invention, as described above, the energy width of the forbidden band of the inner insulating film is larger than the energy width of the forbidden band of the outer insulating film. (FIG. 2) does not exist, and carrier electrons e- or holes h+ injected into the insulating film can easily pass through the insulating film, making it difficult for charge to accumulate at the interface of the insulating film. Furthermore, even if charge is accumulated, this charge is easily swept out of the insulating film by fluctuations in the voltage applied to the insulating film, making it difficult for charge to accumulate in the insulating film. Due to the increase in internal electric field due to the accumulation of
多層絶縁膜のうちの特定の層に局所的に高電界が印加さ
れることがないので、絶縁破壊が起こりにくく、電圧ス
トレスによる耐圧劣化による信頼性の低下を極めて起こ
しにくい。Since a high electric field is not locally applied to a specific layer of the multilayer insulating film, dielectric breakdown is less likely to occur, and reliability is extremely unlikely to deteriorate due to breakdown voltage deterioration due to voltage stress.
実施例 １
第３図は１本発明の一実施例の多層絶縁膜を誘電体とし
て用いたＭＯＳキャパシタの断面図である。Embodiment 1 FIG. 3 is a sectional view of a MOS capacitor using a multilayer insulating film as a dielectric material according to an embodiment of the present invention.
第３図において、１はＳｉ基板、２はＳＬ、Ｎ。In FIG. 3, 1 is a Si substrate, 2 is SL, and N is N.
膜、３はＳ ｉｏ、膜、４はＴａ、Ｏｓ （酸化タンタ
ル）膜、５はＷ（タングステン）電極を示す、キャパシ
タは、ｗｉａ極５とＳｉ基板１の間に形成される。A capacitor is formed between the wia electrode 5 and the Si substrate 1. 3 is a Sio film, 4 is a Ta, Os (tantalum oxide) film, and 5 is a W (tungsten) electrode.
本実施例では、まず、ＳＬ基板１上にＣＶＤ法により５
１３Ｎ４膜２を厚さ約２０〜６０人形成し、その上にＴ
ａ２Ｏ，膜４をスパッタ法により厚さ約５０〜３５０人
形成した後、９５０℃の酸化性雰囲気にて熱処理するこ
とにより、ＴａｔＯｓ膜４を問うして酸化種が拡散され
、ＳＬ、Ｎ、膜２が酸化され、ＳＬ、Ｎ。In this example, first, 5
13N4 film 2 is formed to a thickness of about 20 to 60 layers, and T
After forming the TatOs film 4 to a thickness of about 50 to 350 layers by sputtering, heat treatment is performed in an oxidizing atmosphere at 950°C, thereby oxidizing species are diffused into the TatOs film 4, and the SL, N, and 2 is oxidized to SL,N.
膜２とＴａ、Ｏｓ膜４の界面に極薄の厚さ約４０Å以下
のＳＬｏ、３が形成された。その後、Ｔａ、Ｏ，膜４の
上にＷ？ｌ！極５を形成した。An extremely thin SLo, 3 having a thickness of about 40 Å or less was formed at the interface between the film 2 and the Ta, Os film 4. After that, W? l! Pole 5 was formed.
各絶縁膜の禁制帯のエネルギー幅は、Ｓｉ、Ｎ。The energy width of the forbidden band of each insulating film is Si and N.
が約５ｅＶ、Ｓｉｎ、が約８ｅＶ、Ｔａ、○、が約４．
２ｅＶであるので、本実施例の多層絶縁膜は、内部の絶
縁膜（ＳｉＯ□膜３）の禁制帯のエネルギー幅が外側の
絶縁膜（Ｓｉ、Ｎ、［２，Ｔａ２０５膜４）の禁制帯の
エネルギー幅より大きくなっているので、第１図のエネ
ルギーバンドの模式図に示すように。is approximately 5 eV, Sin is approximately 8 eV, and Ta is approximately 4.
2 eV, in the multilayer insulating film of this example, the energy width of the forbidden band of the internal insulating film (SiO□ film 3) is greater than the energy width of the forbidden band of the outer insulating film (Si, N, [2, Ta205 film 4). As shown in the schematic diagram of the energy band in Figure 1,
従来の多層絶縁膜に存在した位置エネルギーの谷間が存
在せず、絶縁膜に注入された電子ｅ−またはホールｈ＋
が絶縁膜を容易に通過することができ、絶縁膜界面での
電荷の蓄積を防止することができる。There is no gap in potential energy that existed in conventional multilayer insulating films, and electrons e- or holes h+ injected into the insulating film
can easily pass through the insulating film, and can prevent charge accumulation at the interface of the insulating film.
第５図に１本実施例のキャパシタと、第４図に示した従
来のキャパシタの長期信頼度を比較した結果を示す。長
期信頼度の評価方法としては、一定電圧をキャパシタに
印加して、誘電体が絶縁破壊する時間を測定した。第５
図において、横軸は蓄積電荷量、縦軸はキャパシタが破
壊に至る寿命を示す１図から本実施例の多層絶縁膜は、
従来の多層絶縁膜に比して長期信頼度が高いことがわか
る。これにより得られた結果は、実効電界強度を横軸に
とった場合の結果とほぼ一致する。すなわち、実効電界
強度はキャパシタの単位面積当りの容量をＳｉｎ、膜の
膜厚に換算して、このＳｉｎ、換算膜厚でキャパシタへ
の印加電圧を割ることによって得られる。従って、実効
電界強度は、単位面積当りのキャパシタに蓄積されてい
る電荷量に比例している０例えば、１００時間で破壊す
るキャパシタの実効電界強度は、本実施例の５１３Ｎ、
／ｓｉｏ、／Ｔａ２ｏｓ３層絶縁膜の場合、１４〜１５
ＭＶ／備であるが、従来（１）Ｓｉｎ、／５ｉａＮ、／
ＳｉＯ，（７）場合、１０〜ＩＩＭＶ／Ｃ！ｌである。FIG. 5 shows the results of comparing the long-term reliability of the capacitor of this embodiment and the conventional capacitor shown in FIG. 4. As a method for evaluating long-term reliability, a constant voltage was applied to the capacitor and the time required for dielectric breakdown of the dielectric was measured. Fifth
In the figure, the horizontal axis is the amount of accumulated charge, and the vertical axis is the life span of the capacitor until it breaks down. From Figure 1, the multilayer insulating film of this example is
It can be seen that the long-term reliability is higher than that of conventional multilayer insulation films. The results obtained here almost agree with the results obtained when the effective electric field strength is plotted on the horizontal axis. That is, the effective electric field strength can be obtained by converting the capacitance per unit area of the capacitor into Sin, the film thickness of the film, and dividing the voltage applied to the capacitor by this Sin, the film thickness. Therefore, the effective electric field strength is proportional to the amount of charge stored in the capacitor per unit area. For example, the effective electric field strength of a capacitor that breaks down in 100 hours is 513N in this example,
/sio, /Ta2os 3-layer insulating film: 14 to 15
MV/Bei, but conventionally (1) Sin, /5iaN, /
For SiO, (7), 10~IIMV/C! It is l.
従って、同一寿命のキャパシタに蓄積できる電荷量も約
１４／１０＝１．４倍だけ本実施例の３層絶縁膜が多い
といえる。Therefore, it can be said that the amount of charge that can be stored in a capacitor with the same lifetime is approximately 14/10=1.4 times larger in the three-layer insulating film of this embodiment.
第６図に１本実施例の多層絶縁膜に、長時間ストレス電
圧の印加による耐圧劣化の結果を示す。FIG. 6 shows the results of breakdown voltage deterioration due to long-term application of stress voltage to the multilayer insulating film of this example.
この図では、横軸にストレス電圧印加時間、縦軸にリー
ク電流密度を示している。本実施例のｓｉ。In this figure, the horizontal axis shows stress voltage application time, and the vertical axis shows leakage current density. si of this example.
Ｎ ４／ Ｓ ｉＯ−／ Ｔ ａ −Ｏｓ構造の３層絶
縁膜ニＩＯＭＶ／ａ１１の電界を印加するとリーク電流
密度は順方向、逆方向ともストレス電圧印加時間と共に
むしろ減少する方向であり、ストレス電圧印加に伴うリ
ーク電流の増加はなく極めて安定である。When an electric field of IOMV/a11 is applied to a three-layer insulating film with a N4/SiO-/Ta-Os structure, the leakage current density tends to decrease with the stress voltage application time in both the forward and reverse directions, and the stress voltage The leakage current does not increase with application and is extremely stable.
以上示した結果から、本実施例のＳ １３ Ｎ ４ ／
Ｓｉｎｇ／Ｔａ５ｋｓ構造の３層絶縁膜を誘電体として
用いたキャパシタの絶縁破壊に対する長期信頼度は優れ
ており、また、耐圧劣化も生じないことがわかり、欠陥
密度の少ない、長期信頼度の優れたキャパシタ用絶縁膜
が得られた。From the results shown above, it can be seen that S 13 N 4 /
A capacitor using a three-layer insulating film with a Sing/Ta5ks structure as a dielectric has excellent long-term reliability against dielectric breakdown, and also shows no breakdown voltage deterioration, resulting in a capacitor with low defect density and excellent long-term reliability. An insulating film for a capacitor was obtained.
本実施例の多層絶縁膜は、Ｓ Ｌ３ Ｎ ４ ／ Ｓ
ｉ Ｏ２／Ｔａ、Ｏ，構造であったが、この他例えば■
Ｔａ、Ｏ。The multilayer insulating film of this example is S L3 N 4 / S
i O2/Ta, O, structure, but in addition, for example ■
Ta, O.
／Ｓｉｎ、／Ｔａ、Ｏ，、■５Ｌ３Ｎ４／Ｓｉｎ、／Ｓ
Ｌ、Ｎ、、■Ｔａ、Ｏ，／５Ｌ３Ｎ、／ＴａｔＯｓ、■
Ｔａ、０５／Ｓｉ３Ｎ４／５ｉｏｚ／ＴａｘＯｓ など
の多層膜を用いてもよい。この場合も、やはり低欠陥か
つ高信頼性の絶縁膜が得られた。/Sin, /Ta,O,, ■5L3N4/Sin, /S
L, N, ■Ta, O, /5L3N, /TatOs, ■
A multilayer film such as Ta, 05/Si3N4/5ioz/TaxOs may also be used. In this case as well, an insulating film with low defects and high reliability was obtained.
実施例 ２
実施例１では、Ｓｉ基体上に本発明の多層絶縁膜を形成
した例を示したが、本実施例２では、多結晶Ｓｉ膜上に
形成した例を示す。すなわち、本実施例では、Ｓｉ基板
１上に形成した多結晶Ｓｉ膜１０の上に、実施例１と同
様の構造の多層絶縁膜が設けである。Example 2 Example 1 showed an example in which the multilayer insulating film of the present invention was formed on a Si substrate, but Example 2 shows an example in which it was formed on a polycrystalline Si film. That is, in this example, a multilayer insulating film having the same structure as in Example 1 is provided on a polycrystalline Si film 10 formed on a Si substrate 1.
まず、Ｓｉ基板１上に多結晶Ｓｉ膜１０を形成した後、
５１３Ｎ４膜２をＣＶＤ法により形成して、その上にＴ
ａ２Ｏ，膜４をスパッタ法により形成する。First, after forming a polycrystalline Si film 10 on a Si substrate 1,
513N4 film 2 is formed by CVD method, and T
A2O film 4 is formed by sputtering.
その後、９５０℃の酸化性雰囲気において酸化すること
により、Ｓｉ、Ｎ４膜２とＴａ、Ｏ，膜４の界面に５１
０２膜３が形成される。その後、Ｗ電極５をＴａ２Ｏ，
膜４上に形成して、キャパシタを形成した。本実施例の
キャパシタも、実施例１に示すＳｉ基板上に形成された
キャパシタと同等の低欠陥、高耐圧特性および長期信頼
度を示した。Thereafter, by oxidizing in an oxidizing atmosphere at 950°C, 51
02 film 3 is formed. After that, the W electrode 5 was replaced with Ta2O,
A capacitor was formed on the film 4. The capacitor of this example also exhibited low defects, high breakdown voltage characteristics, and long-term reliability equivalent to the capacitor formed on the Si substrate shown in Example 1.
本実施例の多層膜は、多結晶Ｓｉ膜上に形成した５Ｌ３
Ｎ４／５ｉ０２／Ｔａ２ｏ、構造の多層絶縁膜であった
が、この他例えば■’ｒａ＊ｏｉ／ＳｉＯ，／Ｔａ、０
５、■５Ｌ３Ｎ４／５ｉＯｚ／５ｉａＮ＊−■Ｔａ２０
５ ／ Ｓ Ｌ３ Ｎ ４ ／ Ｔ ａ、 ｏ ５、■
Ｔａ２ｏ、／５ｉｉＮ４／ＳｉＯ□／Ｔａ、Ｏ，などの
多層膜を用いても、やはり低欠陥かつ亮信頼性の絶縁膜
が得られた。本実施例の構造を用いると、極めて信頼度
の高い、しかも高容量のキャパシタをメモリデバイスの
素子領域上や分離絶縁膜上に形成することが可能となり
、メモリデバイスの高集積化に極めて有利である。The multilayer film of this example is a 5L3 film formed on a polycrystalline Si film.
It was a multilayer insulating film with a structure of N4/5i02/Ta2o, but in addition, for example, ■'ra*oi/SiO, /Ta, 0
5, ■5L3N4/5iOz/5iaN*-■Ta20
5 / S L3 N 4 / T a, o 5, ■
Even when a multilayer film such as Ta2o, /5iiN4/SiO□/Ta, O, etc. was used, an insulating film with low defects and high reliability was still obtained. By using the structure of this example, it is possible to form an extremely reliable and high-capacity capacitor on the element region of a memory device or on an isolation insulating film, which is extremely advantageous for increasing the integration of memory devices. be.
さらに１本発明は、内部の絶縁膜の禁制帯のエネルギー
幅が外側の絶縁膜の禁制帯のエネルギー幅より大きい構
造を基本とするが、これらの絶縁膜の外側あるいは間に
禁制帯のエネルギー幅の大きい又は小さい絶縁膜を設け
ても、この絶縁膜の膜厚が本発明による作用を阻害しな
いほど薄ければ支障がない。Furthermore, the present invention is based on a structure in which the energy width of the forbidden band of the internal insulating film is larger than the energy width of the forbidden band of the outer insulating film, but the energy width of the forbidden band outside or between these insulating films is Even if an insulating film with a large or small value is provided, there is no problem as long as the thickness of the insulating film is thin enough not to impede the effect of the present invention.
本発明によれば、欠陥密度が少なく、かつ高耐圧で長期
信頼性の高い多層絶縁膜を提供でき、小面積、大容量の
キャパシタを形成できるので、ＬＳＩの集積化に大きな
効果がある。According to the present invention, a multilayer insulating film with low defect density, high breakdown voltage, and high long-term reliability can be provided, and a capacitor with a small area and large capacity can be formed, which is highly effective in integrating LSIs.
第１図は本発明の一実施例の多層絶縁膜のエネルギーバ
ンドの模式図、第２図は従来の多層絶縁膜のエネルギー
バンドの模式図、第３図は本発明の一実施例の多層絶縁
膜を誘電体として用いたＭＯＳキャパシタの断面図、第
４図は従来の多層絶縁膜を誘電体として用いたキャパシ
タの断面図。
第５図は本発明と従来の多層絶縁膜の長期信頼度の比較
結果を示す図、第６図は本発明の多層絶縁膜のリーク電
流密度のストレス印加時間依存性を示す図、第７図は本
発明の別の実施例の多層絶縁膜を形成したキャパシタの
断面図である。
１・・・Ｓｉ基板
２．７・・・Ｓｉ３Ｎ、膜
３．６，８・・・Ｓ ｉ Ｏ、膜
４−＝ Ｔａ２ｏｓ膜
５・・・Ｗｆｆｉ極
９・・・多結晶Ｓｉ電極
１０・・・多結晶５ｉｌｌｊｉFIG. 1 is a schematic diagram of the energy band of a multilayer insulation film according to an embodiment of the present invention, FIG. 2 is a schematic diagram of the energy band of a conventional multilayer insulation film, and FIG. FIG. 4 is a cross-sectional view of a MOS capacitor using a film as a dielectric, and FIG. 4 is a cross-sectional view of a capacitor using a conventional multilayer insulating film as a dielectric. Figure 5 is a diagram showing the comparison results of the long-term reliability of the present invention and the conventional multilayer insulation film, Figure 6 is a diagram showing the stress application time dependence of the leakage current density of the multilayer insulation film of the invention, and Figure 7 FIG. 2 is a cross-sectional view of a capacitor formed with a multilayer insulating film according to another embodiment of the present invention. 1... Si substrate 2.7... Si3N, film 3.6, 8... SiO, film 4-= Ta2os film 5... Wffi pole 9... Polycrystalline Si electrode 10...・Polycrystalline 5illji
Claims (1)
部の膜の禁制帯のエネルギー幅が外側の膜の禁制帯のエ
ネルギー幅より大きいことを特徴とする多層絶縁膜。1. A multilayer insulating film formed by stacking a plurality of insulating films, characterized in that the energy width of the forbidden band of the inner film is larger than the energy width of the forbidden band of the outer film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7124586A JPS62229965A (en) | 1986-03-31 | 1986-03-31 | Multilayered insulating film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7124586A JPS62229965A (en) | 1986-03-31 | 1986-03-31 | Multilayered insulating film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62229965A true JPS62229965A (en) | 1987-10-08 |
Family
ID=13455117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7124586A Pending JPS62229965A (en) | 1986-03-31 | 1986-03-31 | Multilayered insulating film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62229965A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019527476A (en) * | 2016-07-14 | 2019-09-26 | インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ | Inductor structure and method of forming inductor structure |
-
1986
- 1986-03-31 JP JP7124586A patent/JPS62229965A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019527476A (en) * | 2016-07-14 | 2019-09-26 | インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ | Inductor structure and method of forming inductor structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5189503A (en) | High dielectric capacitor having low current leakage | |
| JP3076507B2 (en) | Semiconductor device, semiconductor integrated circuit device, and method of manufacturing the same | |
| US5187557A (en) | Semiconductor capacitor with a metal nitride film and metal oxide dielectric | |
| JPS60153158A (en) | Manufacture of semiconductor device | |
| JP2829023B2 (en) | Capacitors for semiconductor integrated circuits | |
| JPH0558266B2 (en) | ||
| TW200818464A (en) | Capacitor, method of producing the same, semiconductor device, and liquid crystal display device | |
| JPH0685193A (en) | Semiconductor device | |
| JPS62229965A (en) | Multilayered insulating film | |
| JP3182889B2 (en) | Ferroelectric device | |
| JPS5911663A (en) | Manufacture of capacitor for semiconductor device | |
| JPH0438862A (en) | Semiconductor integrated circuit device | |
| JP2796293B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS60107854A (en) | Capacitor | |
| JPS6480060A (en) | Semiconductor integrated circuit device | |
| JPS59175153A (en) | Semiconductor integrated circuit | |
| JPH0414862A (en) | Semiconductor device | |
| EP1020896A1 (en) | Integrated circuit device with composite oxide dielectric | |
| JPS59161861A (en) | Semiconductor device | |
| JPH04179265A (en) | Manufacture of semiconductor device | |
| KR920010201B1 (en) | Semidonductor device and method for manufacturing of the same | |
| JPS5911665A (en) | Semiconductor device | |
| JPS5814537A (en) | Manufacture of semiconductor device | |
| JPH03108752A (en) | Semiconductor device | |
| JPH0456160A (en) | Semiconductor device |