JPS62229957A - Method for wiring of semiconductor device - Google Patents

Method for wiring of semiconductor device

Info

Publication number
JPS62229957A
JPS62229957A JP7098086A JP7098086A JPS62229957A JP S62229957 A JPS62229957 A JP S62229957A JP 7098086 A JP7098086 A JP 7098086A JP 7098086 A JP7098086 A JP 7098086A JP S62229957 A JPS62229957 A JP S62229957A
Authority
JP
Japan
Prior art keywords
wiring
cvd
gas
laser
cvd gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7098086A
Other languages
Japanese (ja)
Other versions
JPH0626236B2 (en
Inventor
Mikio Hongo
幹雄 本郷
Katsuro Mizukoshi
克郎 水越
Junzo Azuma
淳三 東
Takeoki Miyauchi
宮内 建興
Hirotani Saitou
斎藤 啓谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61070980A priority Critical patent/JPH0626236B2/en
Publication of JPS62229957A publication Critical patent/JPS62229957A/en
Publication of JPH0626236B2 publication Critical patent/JPH0626236B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To repair a defective part while wirings are crossed without having a short circuit by a method wherein a wiring is formed by performing a laser CVD, and an insulating film is locally formed between crossing wirings. CONSTITUTION:A chip is placed in CVD gas 5 atmosphere in which a wiring will be formed. On this chip, a window 6 is formed on the connecting part in advance, an additional wiring 8 is formed while a focussed laser beam 7 to be used to deposit a wiring material by dissolving CVD gas, is being projected in a scanning manner, and the connection of 6a and 6b is completed. Then, the CVD gas 5 to be used to deposit the wiring material is exhausted, the CVD material gas 9 to be used to deposit an insulating material is introduced, and the laser beam 7 is made to irradiate scanningly on the crossing part of the additional wiring 8. As a result, the CVD gas 9 is dissolved, and an insulating film 10 is formed. Then, the CVD gas 9 is exhausted again, the CVD gas 5 to be used to deposit the wiring material is introduced, and an additional wiring 11 crossing the additional wiring 8 is formed while the laser beam is being projected through the intermediary of the insulating film 10 on the additional wiring 8.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の表面に配線を付加する方法に係り
、特に試作した半導体装置をに部分的な不良が存在する
場合に不良箇所を特定したり補修するのに好適な配線付
加方法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for adding wiring to the surface of a semiconductor device, and in particular, to a method for identifying a defective location when a prototype semiconductor device has a partial defect. This invention relates to a wiring addition method suitable for repairing or repairing.

〔従来の技術〕[Conventional technology]

近年、半導体装置は微細化、高集積化が著しく製作した
半導体装置が設計通りに動作することは少なく、チップ
上の配線を切断したり、キ意の部分を接続することによ
り不良箇所を特定したり、あるいは補修することにより
暫定的に完全な動作が得られる様にして特性を評価する
ことが行なわれている。このうち、任意の箇所を接続す
る方法としてアプライド・フィジックス・レター39(
12)(1981年)第957頁から第959頁(Ap
pliθdphysics Letter 59 (1
2) (1981) pp957〜959 。
In recent years, semiconductor devices have become much smaller and more highly integrated, making it rare for semiconductor devices manufactured to operate as designed. Characteristics are evaluated by temporarily obtaining complete operation by repairing or repairing the device. Among these, Applied Physics Letter 39 (
12) (1981) pp. 957-959 (Ap
pliθdphysics Letter 59 (1
2) (1981) pp957-959.

あるいはエクステント・アブストラクト・オン・f−セ
ブンティーンスーコンファレンス・オン・ソリッド・ス
テート・デバイス・アンド・マテリアルズ(1985年
)第193頁から第196頁(Extend−ed  
A’bstracts  of  the  17th
  Conference  on  5olidSt
ate  Devices  and  Materi
als  、  Tokyo  、  1985pp1
93〜196などで、レーザCVDにより局所的に配線
を付加形成する技術が論じられている。
or Extend-ed Abstracts on Seventeenth Conference on Solid State Devices and Materials (1985), pp. 193-196.
A'bstructs of the 17th
Conference on 5solidSt
ate Devices and Materi
als, Tokyo, 1985pp1
No. 93-196, etc., discuss techniques for locally forming additional wiring by laser CVD.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術は、複数の配線が交差する点については配
慮がされておらず、交差させた場合には短絡してしまい
、本来の目的が達成できない。また、交差を避けるため
には適用範囲が限定されてしまうという問題点があった
The above-mentioned conventional technology does not take into account the points where a plurality of wires intersect, and when they intersect, a short circuit occurs and the original purpose cannot be achieved. Furthermore, there is a problem in that the scope of application is limited in order to avoid intersections.

本発明の目的は、複数の配線が交差しても短絡すること
なくチップ上の任意の箇所を接続できる半導体装置の配
線方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring method for a semiconductor device that can connect arbitrary locations on a chip without causing short circuits even when a plurality of wiring lines intersect.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、交差する配線の間に局所的に絶縁石を形成
することにより、達成される。
The above object is achieved by forming insulating stones locally between the intersecting wires.

〔作用〕 即ち、まず下層となる配線をレーザCVDKより配線を
形成するため材料ガス雰囲気でレーザ光を照射して形成
し、その後材料ガスを交換して交差する部分を含む周辺
部に、同じくレーザCVDにより絶縁層を形成する。し
かる後に下層配線と交差する配線を絶縁層上に形成する
ことにより、上下配線は互いに絶縁されていて短絡する
ことがない。
[Operation] That is, first, the wiring to be the lower layer is formed by irradiating laser light in a material gas atmosphere to form the wiring by laser CVDK, and then the material gas is exchanged and the peripheral area including the crossing portion is irradiated with the same laser. An insulating layer is formed by CVD. Thereafter, by forming a wiring that intersects with the lower layer wiring on the insulating layer, the upper and lower wirings are insulated from each other and will not be short-circuited.

〔実施例〕〔Example〕

以下、本発明の実施例を図に従い説明する。第1図は本
発明の一実施例の手順を説明するものである。まず第1
図(α)に示す様K S、、基板1上に5=02膜2を
介して配線層3が形成され、パシベーション膜4が全面
に形成されたチップを、配線形成のためのCVDガス5
雰囲気中に載置する。このチップには、接続を要する部
分に予かじめ窓部6が形成されている。なお図では説明
上不要な部分、例えば拡散層などは省略しである。ここ
で、CVDガス5を分解して配線材料を析出させるため
のレーザ光7を集光照射しつつ矢印で示す方向へ走査さ
せる。これは、レーザ光7を移動させても、チップを移
動させても良い。接続を要する部分(図中の6αから6
bまで)の走査を終了した時点でレーザ光7の照射を停
止することにより、第1図(b)に示す様に付加配線8
が形成され、6αと6bの接続が完了する。次に配線材
料を析出するためのCVDガス5を排出し、絶縁材料を
析出させるためのCVD材料ガス9を導入して第1[1
U(0)に示す様に付加配線8の交差部分にレーザ光7
を、少なくとも交差部分を覆う様に走査しつつ照射する
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 explains the procedure of one embodiment of the present invention. First of all
As shown in FIG.
Place it in the atmosphere. This chip has a window 6 formed in advance at a portion where connection is required. Note that in the figure, unnecessary parts such as a diffusion layer are omitted for the sake of explanation. Here, the laser beam 7 for decomposing the CVD gas 5 and depositing the wiring material is focused and irradiated and scanned in the direction shown by the arrow. This may be done by moving the laser beam 7 or by moving the chip. Parts that require connection (6α to 6 in the diagram)
By stopping the irradiation of the laser beam 7 at the time when scanning (up to b) is completed, the additional wiring 8 is removed as shown in FIG. 1(b).
is formed, and the connection between 6α and 6b is completed. Next, the CVD gas 5 for depositing the wiring material is discharged, and the CVD material gas 9 for depositing the insulating material is introduced.
Laser beam 7 is applied to the intersection of additional wiring 8 as shown in U(0).
is scanned and irradiated so as to cover at least the intersection.

これKより、CVDガス9が分解され、第1図(d)に
示す様に絶縁層10が形成される。次に再度、CVDガ
ス9を排気して配線材料を析出させるためのCVDガス
5を導入する。第1図(θ)に示す様にしかる後にレー
ザ光7を照射しつつ、付加配線8上の絶縁膜10を介し
て、紙面に垂直方向に走査して付加配置8に交差する付
加配線11を形成する。
Due to this K, the CVD gas 9 is decomposed and an insulating layer 10 is formed as shown in FIG. 1(d). Next, the CVD gas 9 is exhausted again, and the CVD gas 5 for depositing the wiring material is introduced. As shown in FIG. 1 (θ), the additional wiring 11 intersecting the additional arrangement 8 is then scanned in the direction perpendicular to the plane of the paper through the insulating film 10 on the additional wiring 8 while irradiating the laser beam 7. Form.

ここで、どクシペーション膜4の窓あけはりソグラフィ
技術を用いたエツチングの他に、レーザ加工、イオンビ
ーム加工等を適用することにより達成できる。付加配線
8,110形成に用いるCVDガス5として5LH4と
ドーパントガス、例えばB。AS。
Here, in addition to etching using a window opening lithography technique in the doxipation film 4, laser processing, ion beam processing, etc. can be applied. 5LH4 and a dopant gas such as B as the CVD gas 5 used for forming the additional wirings 8 and 110. A.S.

B(CHi)sなどとの混合ガスを使用することにより
、不純物がドープされた多結晶S=配線が、レーザ光7
としてArレーザを照射することにより形成できる。ま
た、絶縁膜10を形成するCVDガス9として5LHa
とN20の混合ガスを使用することKより5LO2膜が
形成できる。レーザ光としては付加配線の形成と同じ(
Arレーザを使用する。
By using a mixed gas with B(CHi)s etc., the polycrystalline S=wiring doped with impurities is exposed to the laser beam 7.
It can be formed by irradiating Ar laser as a method. Furthermore, 5LHa is used as the CVD gas 9 for forming the insulating film 10.
A 5LO2 film can be formed from K by using a mixed gas of K and N20. The laser beam is the same as the formation of additional wiring (
Use Ar laser.

以上の他、配線材料として幻を析出させる場合はAJ、
 (CHx )iとArレーザの第2高調波、cdを析
出させる場合はCd (CHI )2とArレーザの第
2高調波、Maを析出させる場合はMo (CO) a
とArレーザ、Wを析出させる場合にはW(Co)6と
Arレーザ、N1を析出させる場合にはNi (CO)
4とにレーザ等の組合せを、また絶縁材料として)d、
20sを析出させる場合には)−L (CHs ) s
とN20の混合ガスとArレーザの第2高調波を、Mo
Osを析出させる場合にはMe (Co )4と02の
混合ガスとArレーザを、WO2を析出させる場合には
W(Co)6と02の混合ガスとArレーザ等の組合せ
を使用することができるが、本発明はこれらに限定され
るものではない。
In addition to the above, when depositing phantom as a wiring material, AJ,
(CHx )i and the second harmonic of the Ar laser, Cd (CHI)2 and the second harmonic of the Ar laser when depositing CD, and Mo (CO) a when depositing Ma.
and Ar laser, W(Co)6 and Ar laser when depositing W, and Ni (CO) when depositing N1.
4 and a combination of a laser, etc., and as an insulating material) d,
When precipitating 20s)-L (CHs)s
The second harmonic of the Ar laser and the mixed gas of N20 and Mo
When depositing Os, a combination of a mixed gas of Me(Co)4 and 02 and an Ar laser can be used, and when depositing WO2, a combination of a mixed gas of W(Co)6 and 02 and an Ar laser can be used. However, the present invention is not limited thereto.

次に本発明の別な実施例についてその処理手順を第2図
に示す。まず第2図(α)は第1図(α)と同じ<SL
L板1上に5L(h膜2を介して配線層3が形成され、
バシベーシ目ン膜4が全面に形成されたチップが配線材
料を析出させるためのCVDガス5の雰囲気中に置かれ
る。このチップには配線接続を要する部分に予め窓部6
が形成されている。
Next, FIG. 2 shows a processing procedure for another embodiment of the present invention. First, Figure 2 (α) is the same as Figure 1 (α) <SL
A wiring layer 3 is formed on the L plate 1 via the 5L (h film 2),
A chip on which a perforation film 4 is formed on the entire surface is placed in an atmosphere of CVD gas 5 for depositing wiring material. This chip has a window 6 in advance in the area where wiring connection is required.
is formed.

なお図には、説明上不要部分は省略しである。ここで、
CVDガス5を分解して配線材料を析出させるためのレ
ーザ光7を集光照射1つつ走査する。
Note that parts unnecessary for explanation are omitted in the figure. here,
The laser beam 7 for decomposing the CVD gas 5 and depositing the wiring material is scanned with one focused irradiation.

第1図(α)では紙面に垂直方向に走査させている。In FIG. 1 (α), scanning is performed in a direction perpendicular to the plane of the paper.

接続に必要な部分へのレーザ照射が終了した時点でレー
ザ照射を停止することにより、付加配fs8が形成され
る。次に配線材料を析出させるためのCVDガス5を排
出し、02ガスあるいは乾燥空気12を導入して、第2
図(b)に示す様に付加配線8の交差部分にレーザ光7
を少な(とも交差部分な&5様に走査しつつ照射する。
The additional distribution fs8 is formed by stopping the laser irradiation when the laser irradiation to the portion necessary for connection is completed. Next, the CVD gas 5 for depositing the wiring material is discharged, 02 gas or dry air 12 is introduced, and the second
As shown in Figure (b), the laser beam 7 is applied to the intersection of the additional wiring 8.
Irradiate while scanning in a small number (both intersecting parts) in a &5 manner.

これにより、第2図(C)に示す様にレーザ光7を照射
された付加配線80表面部分に酸化皮膜13が形成され
る。次に02ガスあるいは乾燥空気12を排出し、配線
材料を析出させるためのCVDガス5を導入する。しか
る後に、第2図(d)に示す様にレーザ光7を集光照射
しつつ矢印で示す方向へ走査させる。これにより、第2
図(θ)に示す様に付加配I!8と酸化皮膜13を介し
て交差する付加配線11を形成することができる。ここ
で、配線材料を析出するためのCVD材料ガスとレーザ
については前に述べた組合せを用いることができ、また
酸化皮膜を形成するためには02ガス(あるいは乾燥空
気)と加熱することのできるいかなるレーザとの組合せ
でも可能である。
As a result, an oxide film 13 is formed on the surface portion of the additional wiring 80 irradiated with the laser beam 7, as shown in FIG. 2(C). Next, the 02 gas or dry air 12 is discharged, and the CVD gas 5 for depositing wiring material is introduced. Thereafter, as shown in FIG. 2(d), the laser beam 7 is focused and irradiated and scanned in the direction shown by the arrow. This allows the second
As shown in the figure (θ), additional distribution I! Additional wiring 11 can be formed which intersects with 8 through the oxide film 13. Here, the combination mentioned above can be used for the CVD material gas and laser to deposit the wiring material, and to form the oxide film, it can be heated with 02 gas (or dry air). A combination with any laser is possible.

以上、実施例で述べた方法はウエノ・あるいはチップを
CVDチャンバ内に挿入し一定圧力までCVDガスある
いは酸素を導入した後、レーザを照射して配線あるいは
絶縁膜、酸化皮膜を形成するものであり、CVDガスあ
るいは酸素の導入、排気を何回か繰返えして必要な配線
(絶縁膜を含む)を形成するものである。
The method described in the examples above involves inserting Ueno or a chip into a CVD chamber, introducing CVD gas or oxygen to a certain pressure, and then irradiating it with a laser to form wiring, an insulating film, or an oxide film. , introduction of CVD gas or oxygen, and evacuation are repeated several times to form necessary wiring (including an insulating film).

また、これ以外に、同じくウエノ・あるいはチップをC
VDチャンバ内に挿入し、チャンバ内を常圧排気しなが
らノズル等でCVDガスあるいは酸素などを吹き付けな
からレーザを照射して配線。
In addition to this, you can also use Ueno or chips.
Insert it into a VD chamber, and while evacuating the chamber to normal pressure, spray CVD gas or oxygen with a nozzle, etc., then irradiate it with laser and wire.

絶縁膜あるいは酸化膜を形成することができる。An insulating film or an oxide film can be formed.

この場合は、バルブ操作により吹き出させるガスの種類
を変えるだけで、配線と絶縁膜の切換えができる。(切
換えに要する時間は短いが、CVDガスのムダが多い。
In this case, the wiring and insulating film can be switched simply by changing the type of gas blown out by operating the valve. (The time required for switching is short, but a lot of CVD gas is wasted.

)当然、時間、CVDガス滝*iを除けば、得られる効
果は同じである。
) Of course, except for time and CVD gas waterfall*i, the obtained effects are the same.

なお、今までCVDガスと述べてきたものは、反応ガス
および必要に応じて使用されるバッファの混合ガスの意
味である。
Note that what has been described as CVD gas so far means a mixed gas of a reaction gas and a buffer used as necessary.

また、交差する配線が異なる材料(例えば下層が多結晶
SL配配線上上層幻配m)の場合でも、さらには交差す
る配線のおのおのおよび絶縁層を形成するのに異なるレ
ーザを使用する場合についても本発明に含まれる。
In addition, even when the intersecting wirings are made of different materials (for example, the lower layer is polycrystalline SL wiring and the upper layer phantom wiring), and even when different lasers are used to form each of the intersecting wirings and the insulating layer, Included in the present invention.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、複数の配線を短絡することなく交差さ
せながらLSIチップ上の任意の箇所を接続できるので
、半導体装舒に不良が存在する場合に、不良箇所の特定
が確実に行なえる。また、完全な動作が得られる様に補
修する場合においても、配線上の不良については事実上
制限な(補修が行える効果がある。
According to the present invention, it is possible to connect arbitrary locations on an LSI chip while crossing a plurality of wires without short-circuiting them, so that if a defect exists in a semiconductor device, the defective location can be reliably identified. Furthermore, even when repairing to ensure perfect operation, there is virtually no limit to the number of defects in the wiring.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のレーザ処理方法の手順を説明−する図
、第2図は別な実施例の手順を説明する図である。 1・・・S=基板、2・・・5LO2膜、5・・・配線
層、4・・・パシベーシlン膜、5・・・配線材料を析
出するためのCVDガス、6・・・窓部、7・・・レー
ザ光、8.11・・・付加配線、10・・・絶縁膜、1
3・・・酸化皮膜。 、7=> 代理人弁理士 小  川  勝  男−,7′第 1 
図 第2 図
FIG. 1 is a diagram for explaining the procedure of the laser processing method of the present invention, and FIG. 2 is a diagram for explaining the procedure of another embodiment. 1...S=substrate, 2...5LO2 film, 5...wiring layer, 4...passivation film, 5...CVD gas for depositing wiring material, 6...window Part, 7... Laser light, 8.11... Additional wiring, 10... Insulating film, 1
3... Oxide film. , 7 => Representative Patent Attorney Katsuo Ogawa -, 7' No. 1
Figure 2

Claims (1)

【特許請求の範囲】 1、半導体装置表面にレーザCVDにより配線を形成し
、交差する配線の間に局所的に絶縁膜を形成することを
特徴とする半導体装置の配線方法。 2、局所的に絶縁膜をレーザCVDにより形成すること
を特徴とする特許請求の範囲第1項記載の半導体装置の
配線方法。 3、交差する配線の一方の表面を酸化雰囲気内でレーザ
加熱により酸化させることを特徴とする特許請求の範囲
第1項記載の半導体装置の配線付加方法。
Claims: 1. A wiring method for a semiconductor device, characterized in that wiring is formed on the surface of the semiconductor device by laser CVD, and an insulating film is locally formed between the crossing wirings. 2. The wiring method for a semiconductor device according to claim 1, wherein the insulating film is locally formed by laser CVD. 3. The method for adding wires to a semiconductor device according to claim 1, wherein one surface of the intersecting wires is oxidized by laser heating in an oxidizing atmosphere.
JP61070980A 1986-03-31 1986-03-31 Wiring method for semiconductor device Expired - Fee Related JPH0626236B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61070980A JPH0626236B2 (en) 1986-03-31 1986-03-31 Wiring method for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61070980A JPH0626236B2 (en) 1986-03-31 1986-03-31 Wiring method for semiconductor device

Publications (2)

Publication Number Publication Date
JPS62229957A true JPS62229957A (en) 1987-10-08
JPH0626236B2 JPH0626236B2 (en) 1994-04-06

Family

ID=13447182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61070980A Expired - Fee Related JPH0626236B2 (en) 1986-03-31 1986-03-31 Wiring method for semiconductor device

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5182231A (en) * 1988-04-07 1993-01-26 Hitachi, Ltd. Method for modifying wiring of semiconductor device
WO2004086487A1 (en) * 2003-03-26 2004-10-07 Semiconductor Energy Laboratory Co. Ltd. Semiconductor device and method for manufacturing same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62245553A (en) * 1986-04-18 1987-10-26 Hitachi Ltd Magnetic recording and reproducing device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62245553A (en) * 1986-04-18 1987-10-26 Hitachi Ltd Magnetic recording and reproducing device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5182231A (en) * 1988-04-07 1993-01-26 Hitachi, Ltd. Method for modifying wiring of semiconductor device
WO2004086487A1 (en) * 2003-03-26 2004-10-07 Semiconductor Energy Laboratory Co. Ltd. Semiconductor device and method for manufacturing same
JPWO2004086487A1 (en) * 2003-03-26 2006-06-29 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method thereof
US7554117B2 (en) 2003-03-26 2009-06-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7955910B2 (en) 2003-03-26 2011-06-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP4869601B2 (en) * 2003-03-26 2012-02-08 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method of semiconductor device

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