JPS62229863A - Semiconductor element mounting circuit board having sealing frame - Google Patents

Semiconductor element mounting circuit board having sealing frame

Info

Publication number
JPS62229863A
JPS62229863A JP61072070A JP7207086A JPS62229863A JP S62229863 A JPS62229863 A JP S62229863A JP 61072070 A JP61072070 A JP 61072070A JP 7207086 A JP7207086 A JP 7207086A JP S62229863 A JPS62229863 A JP S62229863A
Authority
JP
Japan
Prior art keywords
resin
sealing frame
semiconductor element
circuit board
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61072070A
Other languages
Japanese (ja)
Inventor
Toshihiko Yasue
敏彦 安江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP61072070A priority Critical patent/JPS62229863A/en
Publication of JPS62229863A publication Critical patent/JPS62229863A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/26—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device including materials for absorbing or reacting with moisture or other undesired substances, e.g. getters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To spread a liquid resin, which is potted aud sealed, on the entire surface of the inside of a sealing frame surrounding an element mounting part and to prevent the outflow of the resin beyond the sealing frame, by forming the sealing frame with a thermosetting resin, whose surface layer part is coated with water repelling powder. CONSTITUTION:A thermosetting resin 3 is applied around the semiconduc-torelement mounting part of a circuit board 1 in a frame shape. water repelling powder 4 is sprayed on the surface, heated and hardened. Thus a sealing frame 20 is formed. A semiconductor element 8 is die-bonded to the element mounting part. The pad of the element 8 is bonded to a pattern 5 of the board 1 with with 9 such as gold wire. A liquid resin is potted and sealed in the inside of the sealing frame 20. The resin is heated and hardened. For the thermosetting resin 3 forming the skelton of the sealing frame 20, epoxy resin, phenol resin, melamine resin and modified resin thereof are used. For the water repelling powder 4, the granule body of fluorine based resin or silicon based resin is used.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体素子を搭載し、この半導体素子に対して
封１ト、■樹脂をボッティングさせることにより、当該
半導体素子の封止を行なう直接実装方式に使用するため
の回路基板に関するものである。[Detailed Description of the Invention] (Industrial Application Field) The present invention mounts a semiconductor element, and seals the semiconductor element by bottling the semiconductor element with a resin. The present invention relates to a circuit board for use in a direct mounting method.

（従来の技術） 電子時計あるいは電卓等の半導体素子を使用した各種の
電子＃ｌ″ＪＡでは、その小型化及びｆｉｌｌ化が商品
としての付加価値を高めるための重要な要素となってい
るため、これらの電子ａ１審に組込まれる回路基板に対
して、できるだけ厚さを薄くできるｊ−）　ｔＬ−ａ造
の開発が望まれている。従来のこのような封止構造とし
て採用されているものは、半導体素子を回路基板に直接
ダイボンディングし、半導体素子のバットと回路基板の
パターンとの間を金線等のワイヤーによってボンディン
グして、さらにこれらのＦをエポキシ樹脂等の液状樹脂
によってボッチ４ｆング封止するものである。(Prior Art) In various electronic #1''JA devices using semiconductor elements, such as electronic watches and calculators, miniaturization and filling are important factors for increasing the added value of products. It is desired to develop a j-)tL-a structure that can be made as thin as possible for the circuit boards incorporated in these electronic A1 circuit boards.The conventional sealing structure used is , the semiconductor element is directly die-bonded to the circuit board, the butt of the semiconductor element and the pattern of the circuit board are bonded with a wire such as a gold wire, and these F are bonded using liquid resin such as epoxy resin. It is for sealing.

この封止構造においては、エポキシ樹脂等の液状樹脂に
よって半導体素子をできる限り薄く封１トすること、及
び液状ｖＡ脂の周囲への広がりを防止することが重要で
あり、この点に関し種々な提案がなされている。In this sealing structure, it is important to seal the semiconductor element as thinly as possible with liquid resin such as epoxy resin and to prevent the liquid vA fat from spreading to the surrounding area. Various proposals have been made in this regard. is being done.

すなわち、従来のボ・ンティング封止した液状樹Ｉｆｉ
の周囲への広がりを防ｌ−する構造としては１回路基板
の半導体素子搭載部の周囲に封＋Ｅ枠を設ける構造が採
用されている。ここで使用される封ＩＥ枠としては、 （イ）熱ｎ（ｉ性及び熱硬化性樹脂等から成形した枠状
体（封【ヒ枠）を回路基板Ｅに接着したもの （ロ）スクリーン印刷等の方法によりシリコン樹脂等の
撥水性を有する樹脂からなる枠状体を回路基板上に形成
したもの （ハ）上記（ロ）と同様の方法によりエポキシ樹脂等の
非撥水性の樹脂からなる枠状体を回路ノ＾板］二に形成
したもの （ニ）感光性ソルダーレジスト用ドライフィルムにより
回路基板上に枠状体を形成したものなどがある。That is, the conventional bonding-sealed liquid tree Ifi
A structure in which a sealing frame is provided around the semiconductor element mounting portion of one circuit board has been adopted as a structure for preventing the spread of the semiconductor element to the surrounding area. The sealing IE frame used here is: (a) A frame-like body (sealing frame) molded from thermosetting resin, etc., adhered to the circuit board E; (b) Screen printing. (c) A frame made of a non-water repellent resin such as epoxy resin formed by the same method as (b) above on a circuit board. (2) A frame-shaped body is formed on a circuit board using a dry film for photosensitive solder resist.

しかしながら、上述の各封止枠を使用する場合には、そ
れぞれ以下に示すような問題点がある。However, when using each of the above-mentioned sealing frames, there are problems as shown below.

（発明か解決しようとする問題点） 上記（イ）の熱可塑性及び熱硬化性樹脂等から成形され
る棒状体は、回ｌＦ１基板の半導体搭載部が小さくなる
につれて枠状体の成形が困難になることから、究極の目
的である電子機器の小型化及び傅型化への対応が困難に
なるのである。また、このような枠状体は、回路基板−
ヒに接着剤や接着シート等を使用して接着されるため、
これらの接着剤等が枠状体の接着部分からはみだしてワ
イヤーボンディング部を汚染するから、当該回路基板に
おいてボンディング不良が発生し易いことになる。これ
とは逆に、以、Ｌの接着剤等のはみだしを抑えようとす
ると接着不良を生じ１回路基板と枠状体との間からボッ
ティング封止された液状樹脂が流出することにもなる。(Problem to be solved by the invention) Regarding the rod-shaped body molded from thermoplastic, thermosetting resin, etc. in (a) above, it becomes difficult to mold the frame-shaped body as the semiconductor mounting portion of the F1 board becomes smaller. As a result, it becomes difficult to respond to the ultimate goal of downsizing and increasing the size of electronic devices. In addition, such a frame-like body can be used as a circuit board.
Since it is attached using adhesive or adhesive sheet, etc.
Since these adhesives and the like protrude from the bonded portion of the frame-like body and contaminate the wire bonding portion, bonding defects are likely to occur on the circuit board. On the contrary, if you try to prevent the adhesive of L from spilling out, it will result in poor adhesion and the liquid resin sealed by botting will flow out from between the circuit board and the frame-shaped body. .

さらに、このような棒状体を使用すること自体、この枠
状体を回路基板に接着するまでに多数の工程を必要とし
、製品そのものが高価になるということになる。Furthermore, the use of such a rod-like body itself requires a large number of steps until the frame-like body is bonded to the circuit board, making the product itself expensive.

上記（ロ）のスクリーン印刷等の方法によるシリコン樹
脂等の撥水性を有する樹脂からなる枠状体は、実公昭４
９−４３８７３号、特開昭５３−２０７８号、特開昭５
３−２０７９号、特開昭５５−１３８２４０号公報にお
いて提案されているように、その撥水作用により非常に
優れた封ＩＥ効果を示すが、これらの発明または考案に
より得られる封止枠は１次のような重大な問題がある。The frame-shaped body made of a water-repellent resin such as silicone resin by the above method (b) such as screen printing was
No. 9-43873, JP-A-53-2078, JP-A-Sho 5
As proposed in No. 3-2079 and Japanese Unexamined Patent Publication No. 138240/1983, the sealing frame obtained by these inventions or devices exhibits an extremely excellent sealing IE effect due to its water-repellent action. There are serious issues such as:

第一は、これらの発明または考案におけるシリコン樹脂
等の撥水性を有する樹脂をスクリーン印ＦＩ４等の方法
により回路基板の所定の位置に枠形成し、その後峻化さ
せる工程において、シリコン樹脂等の撥水性を有する樹
脂中の低分子槍の七ツマ−あるいはオリゴマーが浸み出
すことは絶対に避けられないことである。この硬化中に
浸み出した低分子＃よの千ツマ−あるいはオリゴマーは
、それ自体も当然撥水性を有するものであり、これらの
ものか浸み出している部分に対しては、ボッティング封
ｌトされる液状樹脂かはじかれてしまい、その部分は封
！トされない状態になるのである。Firstly, in the process of forming a frame of a water-repellent resin such as silicone resin at a predetermined position on a circuit board by a method such as screen stamping FI4 in these inventions or ideas, and then sharpening it, the water-repellent resin such as silicone resin is It is absolutely unavoidable that low-molecular weight molecules or oligomers in the aqueous resin will ooze out. The low molecular weight molecules or oligomers that ooze out during this curing are naturally water repellent, and the areas where these things ooze out should be sealed with bottling. The liquid resin that was poured was repelled, and that part was sealed! This results in a state where the data cannot be accessed.

第二は、これらの発明あるいは考案におけるシリコン樹
脂等の撥水性を有する樹脂は、樹脂そのものの引裂強度
か小さくしかも接着力も−・般的に小さいため５回路基
板から剥かれ易く、欠落した封１１−枠の一部からポツ
ティング対重した液状樹脂が流れ出してしまい、良好な
封止が行なわれないのである。Second, the water-repellent resins such as silicone resins used in these inventions or ideas have a low tear strength and adhesive strength.5 They are easy to peel off from the circuit board, and the broken seals can be easily removed. - Potting liquid resin flows out from a part of the frame, and good sealing cannot be achieved.

上記（ハ）のスクリーン印刷等の方法によるエポキシ樹
脂等の非撥水性の樹脂からなる枠状体は、実開昭５５−
２５３８１号、実開昭５７−２６５８号、実開昭５７−
１７８４５０号、実開昭５７−２０００３８号公報にお
いて提案されているか、これらの考案の封止枠はボッテ
ィング封止されるエポキシ樹脂等の液状樹脂との親和性
が強いため、その封Ｉト効果は専ら封止枠の高さにより
支配される。そのため、封止枠の高さの微妙な変動ある
いは成形方法によっては避は難い凹凸やボ・ンティング
封１トされる液状樹脂量のばらつき等により、ボッティ
ング封＋ｈ　Ｌ／だ液状樹脂が流出するという欠点があ
る。The frame-shaped body made of non-water repellent resin such as epoxy resin by the above method (c) such as screen printing is
No. 25381, Utility Model No. 57-2658, Utility Model No. 57-
No. 178450 and Japanese Utility Model Application Publication No. 57-200038, the sealing frames of these designs have a strong affinity with liquid resins such as epoxy resins to be sealed by botting, so that their sealing effects can be improved. is dominated exclusively by the height of the sealing frame. Therefore, due to subtle fluctuations in the height of the sealing frame, unevenness that is difficult to avoid depending on the molding method, and variations in the amount of liquid resin to be sealed, liquid resin may leak out. There is a drawback that it does.

上記（ニ）の感光性ソルダーレジスト川ドライフィルム
からなる枠状体は、゛よ公開５７−１８７６８号公報に
おいて提案されているように、この材料もエポキシ樹脂
等の液状樹脂との親和性が強いため、その封止効果は（
ハ）の封止枠と同様に封ｌＩ：枠の高さにより支配され
る。この場合の封止枠の高さの変動は非次に小さいが、
トライフィルムそのものか非常に高価であることが最大
の欠点である。The frame-shaped body made of the photosensitive solder resist dry film described in (d) above has a strong affinity with liquid resins such as epoxy resins, as proposed in Japanese Publication No. 57-18768. Therefore, the sealing effect is (
Similar to the sealing frame c), sealing is controlled by the height of the frame. In this case, the variation in the height of the sealing frame is the next smallest, but
The biggest drawback is that the tri-film itself is very expensive.

このように従来の封１に枠を有する半導体素子ＰＳＳ田
川回路基板、前記従来例（ロ）に示すように、ボッディ
ング封１−される液状樹脂か半導体素子搭載部を囲む封
止枠の内部全面に拡がりきらず、未ｉ４　ＩＩ一部分が
生じること、及びこれとは逆に前記従来例（ハ）（ニ）
に示すようにボッティング封１トされる液状樹脂と半導
体素子搭載部を囲む月１Ｌ枠との親和性が高いために、
ポツティング封！トされる液状樹脂が微妙なボッティン
グ条件の変動により封１Ｆ枠を乗り越えて封止枠外部へ
流出すること、さらに前記従来例（イ）に示すように、
回路基板と封止枠との接着層からボッティング封止され
る液状樹脂か流出することなど半導体素子搭載用回路基
板としての信頼性に係る重大な欠点を有している。その
上、前記従来例（イ）及び（ニ）は、１４　Ｉｆ：枠を
形成する工程が複雑で、しかも材料費か割高であるなど
、実際にこれを採用することは非常に困難である。As shown in the conventional example (b) of the semiconductor element PSS Tagawa circuit board having a frame in the conventional sealing 1, as shown in the conventional example (b), the liquid resin used in the bodding sealing 1 is applied to the entire inner surface of the sealing frame surrounding the semiconductor element mounting area. It does not spread completely and some part of i4 II is generated, and on the contrary, in the conventional examples (c) and (d),
As shown in the figure, the liquid resin used for botting sealing has a high affinity with the monthly 1L frame that surrounds the semiconductor element mounting area.
Potting sealed! In addition, as shown in the conventional example (a) above, the liquid resin to be poured overflows the sealing 1F frame and flows out of the sealing frame due to subtle fluctuations in the botting conditions.
This has serious drawbacks that affect the reliability of the circuit board for mounting semiconductor elements, such as the fact that the liquid resin used for botting-sealing flows out from the adhesive layer between the circuit board and the sealing frame. Moreover, in the conventional examples (a) and (d), the process of forming the 14 If frame is complicated, and the material cost is relatively high, so that it is very difficult to actually employ them.

本発明は、以上のような従来の封止枠を有する半導体素
子搭載用回路基板における各種問題点を解決すべくなさ
れたもので、その目的とするところは、ボッティング封
止されるエポキシ樹脂等の液状樹脂か半導体素子搭載部
を囲む封止枠の内部全面に広がり、【ノかも封止枠を越
えて流出しないような封ＩＥ枠を簡単な構成によって提
供することにある。The present invention has been made in order to solve various problems in the conventional circuit board for mounting semiconductor elements having a sealing frame as described above, and its purpose is to seal the epoxy resin etc. to be sealed by botting. To provide a sealed IE frame with a simple structure in which liquid resin spreads over the entire inside of a sealing frame surrounding a semiconductor element mounting part and does not leak beyond the sealing frame.

Ｃ問題点を解決するための手段） Ｌ記の目的を達成するために、本発明の発明者が鋭意研
究を重ねた結果、次に示す封止枠を有する半導体素子ｐ
５佐川用路基板か、従来のものに比べ格段に優れている
ことを見出した。Means for Solving Problem C) In order to achieve the object of item L, the inventor of the present invention has conducted intensive research and has developed a semiconductor element p having the following sealing frame.
It was discovered that the 5-Sagawa road board is significantly superior to the conventional one.

すなわち１本発明は、゛ト導体素子Ｎｓ載用回路↓（板
の半導体素子搭載部の周囲に形成された封１１：枠（２
０）の表層部が、撥水性粉末（４）により被覆された熱
硬化性樹脂（コ）により形成されてなることを特徴とす
る封Ｉ―枠（２０）を有する半導体素子搭載用回路基板
である。In other words, 1 the present invention provides a circuit for mounting a conductor element Ns ↓ (a seal 11 formed around the semiconductor element mounting portion of the board): a frame (2
A circuit board for mounting a semiconductor element having a sealing I-frame (20), characterized in that the surface layer of 0) is formed of a thermosetting resin (C) coated with a water-repellent powder (4). be.

次に、この発明に掛る手段をより詳細に説明する。Next, the means according to the present invention will be explained in more detail.

本発明における半導体素子搭載用回路基板は。The circuit board for mounting a semiconductor element in the present invention is a circuit board for mounting a semiconductor element.

ＩＣ，ＬＳＩ笠の能動部品を直接搭載することができる
回路ノ＾板を総称するものであり、材質はガラスエポキ
シ樹脂、ポリイミドフィルム等の有機質基板、アルミナ
等のセラミック基板あるいはアルミ等の金属基板等何れ
てもよく、特に限定するものではない。This is a general term for circuit boards on which active components of IC and LSI caps can be directly mounted, and the materials include organic substrates such as glass epoxy resin and polyimide film, ceramic substrates such as alumina, and metal substrates such as aluminum. Any of these may be used, and there is no particular limitation.

この半導体素子搭載用回路基板の半導体素子搭載部は基
板に対して凹部を形成したもの、あるいは形成していな
いものの何れでもよい。The semiconductor element mounting portion of this semiconductor element mounting circuit board may have a recess formed in the substrate or may not have a recess formed therein.

本発明の封！Ｌ枠（２０）は熱硬化性樹１ｍ（：ｌ）に
より形成されるものであるが、その表層部か撥水性粉末
（４）により被覆されていることが特徴である。The seal of the present invention! The L frame (20) is formed of 1 m (:l) of thermosetting resin, and is characterized in that its surface layer is coated with water-repellent powder (4).

この封止枠（２０）の骨格を形成する熱硬化性樹脂（３
）とは、エポキシ樹脂、フェノール樹脂、メラミン樹脂
及びこれらの変性樹脂を総称するものであり、必要に応
じてシリカ、タルク等の充填剤や、着色のための顔料な
どを添加しても差し支えない、また、この封止枠（２０
）の表層部を形成する撥水性粉末（０は、フッ素系樹脂
あるいはシリコン系樹脂のポリマー状態のものを粉粒状
体としたものであり、その粒径等は特に限定するもので
はない。この撥水性粉末（４）は、それ自体既にポリマ
ー状態であるため、従来の撥水性樹脂の硬化過程におい
て認められたような低分子量の七ツマ−あるいはオリゴ
マーの浸み出しは全く起こらない。Thermosetting resin (3) forming the skeleton of this sealing frame (20)
) is a general term for epoxy resins, phenolic resins, melamine resins, and modified resins thereof, and fillers such as silica and talc or pigments for coloring may be added as necessary. , Also, this sealing frame (20
) The water-repellent powder forming the surface layer of the water-repellent powder (0 is a fluorine-based resin or silicone-based resin in the polymer state in the form of powder and granules, and the particle size etc. are not particularly limited. Since the aqueous powder (4) itself is already in a polymer state, no leaching of low molecular weight hexamers or oligomers, which is observed in the curing process of conventional water-repellent resins, occurs.

本発明の封止枠（２０）の骨格を形成する熱硬化性樹１
指（３）は、回路基板との接着性が良く、それ自体の機
械的強度も高いので、−・定の固定形状を有するものと
してのＭ　＋）、枠（２０）を形成する成分としては最
適なものである。特に、エポキシ樹脂は回路ノ＾板との
親和性が高く、最も適している。Thermosetting tree 1 forming the skeleton of the sealing frame (20) of the present invention
Since the finger (3) has good adhesion to the circuit board and has high mechanical strength itself, M +), which has a fixed shape of -. It is the most suitable one. In particular, epoxy resin has a high affinity with circuit boards and is most suitable.

つぎに、本発明の封止枠（２０）の表層部を形成する撥
水性粉末（４）は、それ自体が有する撥水性により、ボ
ッティング封止される液状樹脂をはじくことにより封１
効果を発揮するものである。特に、フッ素系樹脂の粉粒
体は化学的及び物理的な安定性が高く、最も適している
。Next, the water-repellent powder (4) forming the surface layer of the sealing frame (20) of the present invention repels the liquid resin to be sealed by botting due to its own water repellency.
It is effective. In particular, fluororesin powders have high chemical and physical stability and are most suitable.

つぎに、撥水性粉末（４）による被覆の状態については
、第１図の（ａ）に示すように、全表面が完全に覆われ
°Ｃいても、第１図の（ｂ）に示すように、かなり疎な
状態で被覆されていても差し支えない。さらに撥水性粉
末（４）により被覆される部位については、第１図の（
Ｃ）に示すように、熱硬化性樹脂（３）により形成され
る封！Ｅ枠（２０）の頂部付近にのみ撥水性粉末（４）
が被ｍされているものも本発明の範囲に入るものである
。Next, regarding the state of coating with water-repellent powder (4), as shown in Fig. 1(a), even if the entire surface is completely covered at °C, as shown in Fig. 1(b), However, it may be covered in a fairly sparse manner. Furthermore, regarding the area covered with the water-repellent powder (4), see (
As shown in C), a seal formed from thermosetting resin (3)! Water repellent powder (4) only near the top of E frame (20)
Those covered with m are also within the scope of the present invention.

（実施例） 次に本発明の封止枠（２０）を形成する一実施例につい
てより具体的に説明するが１本発明の封止枠（２０）は
以下の実施例に限定されるものではない。(Example) Next, an example of forming the sealing frame (20) of the present invention will be described in more detail, but the sealing frame (20) of the present invention is not limited to the following example. do not have.

まず、熱硬化性樹脂（３）としては、ノボラック型エポ
キシ樹脂を主成分とするソルダーレジストインクを、通
常のスクリーン印刷法あるいはスタンプ法等の方法によ
り、半導体素子搭載用回路基板の半導体素子搭載部の周
囲に枠状に塗布する。First, as the thermosetting resin (3), a solder resist ink containing novolac type epoxy resin as the main component is applied to the semiconductor element mounting area of the circuit board for mounting the semiconductor element by a method such as a normal screen printing method or a stamping method. Apply in a frame around the area.

ついで、この塗布された棒状体の表面にポリテトラフル
オロエチレン（以下ＰＴＦＥと略す）の微粉末を散布す
る。Next, fine powder of polytetrafluoroethylene (hereinafter abbreviated as PTFE) is sprinkled on the surface of the coated rod.

ついで、この回路基板を熱風炉あるいは遠赤外線炉等で
加熱硬化させる。このとき、熱硬化性樹脂（３）に散布
された撥水性粉末（４）は、加熱による熱硬化性樹脂（
３）の低粘化に伴ない、その一部が熱硬化性樹脂（３）
に埋った状態となり、単なる接着よりは強く固着される
。Next, this circuit board is heated and hardened using a hot air oven or a far-infrared oven. At this time, the water-repellent powder (4) sprinkled on the thermosetting resin (3) is removed by heating the thermosetting resin (
As the viscosity of 3) becomes lower, some of it becomes thermosetting resin (3)
The material is buried in the material, and is fixed more strongly than simply adhesive.

このようにして形成された封止枠（２０）を有する半導
体素子搭載用回路基板の半導体素子搭載部に半導体素子
（８）をダイボンディングし、半導体素子（８）のパッ
ドと回路基板のパターン（５）との間を金線等のワイヤ
ー（９）によってワイヤーボンディングした後、封止枠
（２０）の内部へ液状のエポキシ樹脂をボッティング封
！トし、加熱により硬化させたとき、液状のエポキシ樹
脂は第２図に示すように封止枠（２０）の頂部において
大きな接触角を保った状態で硬化するため、ｊＪ止枠（
２０）を乗り越えて周囲へ流れ出すことがない。The semiconductor element (8) is die-bonded to the semiconductor element mounting portion of the semiconductor element mounting circuit board having the sealing frame (20) thus formed, and the pad of the semiconductor element (8) and the pattern ( 5) after wire bonding with a wire (9) such as a gold wire, seal the inside of the sealing frame (20) with liquid epoxy resin! When the liquid epoxy resin is cured by heating, the liquid epoxy resin hardens while maintaining a large contact angle at the top of the sealing frame (20), as shown in Fig. 2.
20) will not flow out to the surrounding area.

（発明の効果） 以上のように本発明の封止枠（２０）を有する半導体素
子搭載用回路基板は、撥水性粉末（４）が封ＩＩ：。(Effects of the Invention) As described above, in the circuit board for mounting a semiconductor element having the sealing frame (20) of the present invention, the water-repellent powder (4) is sealed II:.

枠（２０）の表層部を被覆しているため、その撥水効果
によりＭ＋ｆ−効果が非常に高いこと、撥水性粉末（４
）がポリマー状態であるため化学的に安定であり、低分
子量の千ツマ−あるいはオリゴマーが浸み出さないので
、ボッティング封止される液状樹脂が封止枠（２０）内
に完全に広がること、封止枠（２０）本体か熱硬化性樹
脂（コ）により形成されているのて機械的強度か高くし
かも回路基板との密着性もよ＜ａｍ等が全くないこと、
非常に少量の撥水性粉末（４）で優れた撥水効果か得ら
れるので、封止枠（２０）の高さを低くでき小型化への
対応に向いていること、スクリーン印刷等の方法か採用
できるので安価であることなど、多くの効果かあり産業
ヒ極めて有用である。Since the surface layer of the frame (20) is coated, the M+f- effect is extremely high due to its water-repellent effect, and the water-repellent powder (4
) is in a polymer state and is chemically stable, and low molecular weight polymers or oligomers do not leak out, so the liquid resin to be sealed by botting spreads completely within the sealing frame (20). Since the main body of the sealing frame (20) is made of thermosetting resin (C), it has high mechanical strength and has good adhesion to the circuit board, with no problems such as
Since an excellent water repellent effect can be obtained with a very small amount of water repellent powder (4), the height of the sealing frame (20) can be lowered, making it suitable for miniaturization, and methods such as screen printing. It has many effects, such as being inexpensive and can be adopted, and is extremely useful in industry.

【図面の簡単な説明】[Brief explanation of drawings]

第１図の（ａ）（ｂ）及び（Ｃ）のそれぞれは本発明の
封１ト枠の断面の模式図、第２ＵＡは本発明の封止枠を
有する半導体素子搭載用回路基板に半導体素子を実装し
たのち、液状樹脂によりボ・ンティング封止した状態を
示す部分拡大断面図である。 （以下余白） 符　　　号　　　の　　　説　　　ＩＪＩｌ・・・基板
、２・・・ソルダーレジスト、３・・・熱硬化性樹脂、
４・・・撥水性粉末、５・・・導体パターン、６・・・
ダイバウト、７・・・タイボンドペースト、８・・・半
導体素子、９・・・ワ・イヤー、１０・・・ボッティン
グ月止樹ＩＦｔ、２０・・・封止枠。(a), (b), and (C) of FIG. 1 are schematic cross-sectional views of the sealing frame of the present invention, and 2UA is a schematic cross-sectional view of a semiconductor element mounting circuit board having the sealing frame of the present invention. FIG. 3 is a partially enlarged cross-sectional view showing a state in which the device is bonded and sealed with liquid resin after being mounted. (Left below) Explanation of code IJIl...Substrate, 2...Solder resist, 3...Thermosetting resin,
4... Water repellent powder, 5... Conductor pattern, 6...
Die-bout, 7... Tie bond paste, 8... Semiconductor element, 9... Wire, 10... Botting moon stop tree IFt, 20... Sealing frame.

Claims (1)

【特許請求の範囲】 １）、半導体素子搭載用回路基板の半導体素子搭載部の
周囲に形成された封止枠の表層部が、撥水性粉末により
被覆された熱硬化性樹脂により形成されてなることを特
徴とする封止枠を有する半導体素子搭載用回路基板。 ２）、前記撥水性粉末がフッ素系樹脂粉末あるいはシリ
コン系樹脂粉末であることを特徴とする特許請求の範囲
第１項に記載の封止枠を有する半導体素子搭載用回路基
板。 ３）、前記熱硬化性樹脂がエポキシ樹脂であることを特
徴とする特許請求の範囲１項または第２項に記載の封止
枠を有する半導素子搭載用回路基板。[Claims] 1) The surface layer of the sealing frame formed around the semiconductor element mounting portion of the semiconductor element mounting circuit board is formed of a thermosetting resin coated with water-repellent powder. A circuit board for mounting a semiconductor element having a sealing frame characterized by the following. 2) A circuit board for mounting a semiconductor element having a sealing frame as set forth in claim 1, wherein the water-repellent powder is a fluorine-based resin powder or a silicon-based resin powder. 3) A circuit board for mounting a semiconductor element having a sealing frame according to claim 1 or 2, wherein the thermosetting resin is an epoxy resin.
JP61072070A 1986-03-28 1986-03-28 Semiconductor element mounting circuit board having sealing frame Pending JPS62229863A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61072070A JPS62229863A (en) 1986-03-28 1986-03-28 Semiconductor element mounting circuit board having sealing frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61072070A JPS62229863A (en) 1986-03-28 1986-03-28 Semiconductor element mounting circuit board having sealing frame

Publications (1)

Publication Number Publication Date
JPS62229863A true JPS62229863A (en) 1987-10-08

Family

ID=13478773

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61072070A Pending JPS62229863A (en) 1986-03-28 1986-03-28 Semiconductor element mounting circuit board having sealing frame

Country Status (1)

Country Link
JP (1) JPS62229863A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4881885A (en) * 1988-04-15 1989-11-21 International Business Machines Corporation Dam for lead encapsulation
JPH02142148A (en) * 1988-11-22 1990-05-31 Toshiba Glass Co Ltd Semiconductor sealing method
EP0403783A2 (en) * 1989-06-20 1990-12-27 International Business Machines Corporation High strength low stress encapsulation of interconnected semiconductor devices
JP2018018883A (en) * 2016-07-26 2018-02-01 日本電産株式会社 Electrical equipment

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4881885A (en) * 1988-04-15 1989-11-21 International Business Machines Corporation Dam for lead encapsulation
JPH02142148A (en) * 1988-11-22 1990-05-31 Toshiba Glass Co Ltd Semiconductor sealing method
EP0403783A2 (en) * 1989-06-20 1990-12-27 International Business Machines Corporation High strength low stress encapsulation of interconnected semiconductor devices
JP2018018883A (en) * 2016-07-26 2018-02-01 日本電産株式会社 Electrical equipment

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