JPS62226245A - Memory control system - Google Patents

Abstract

PURPOSE:To shift data at a high speed for processing by changing the contents of a register which sets the head address of each memory circuit having the duplicated addresses. CONSTITUTION:When a memory reading request is produced from a system bus, a comparator 21 of a memory control circuit 20 compares the contents of an address setting circuit 10 and a higher bit of an address and outputs a chip selection signal to a memory circuit 50. Furthermore an address converting circuit 40 converts a lower bit of the address into an address and delivers an address signal to the circuit 50. In such a way, the comparison of addresses is carried out based on the set value of the circuit 10. Therefore a shift is facilitated between two addresses of data just by changing the set value of the circuit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to memory access, and in particular to a memory control method suitable for moving data from one address to another. As a memory control method, JP-A-59-6066
As described in Japanese Patent Application No. 3, the memory is expanded by providing a register indicating which address is to be used for a memory having partially overlapping addresses.

[Problem that the invention seeks to solve]

The above conventional technology does not give any consideration to the movement of data between multiple memory circuits having duplicate addresses, and when moving data from one memory circuit with duplicate addresses to the other memory circuit, first, Move data from one memory circuit of the duplicated address to an address that does not contain f[, and then move the register setting indicating whether to use one of the memory circuits with the duplicated address to the change circuit. There was a problem that such an operation required a lot of processing time.The purpose of the present invention is to solve this problem and to make it possible to change duplicate addresses. By doing so, it is an object of the present invention to provide a memory control method that performs data movement processing 2 at high speed.

[Means for solving problems]

The above purpose is to provide a register for setting the start address of the corresponding memory circuit and a register for setting read and write conditions for each memory circuit with duplicate addresses, and to transfer the duplicate address from one memory circuit to the other memory circuit. When moving data, first change the address of one memory circuit by changing the register settings, then change the register settings of the sixth memory circuit, which has the newly duplicated address, to prohibit reading and writing. While performing address conversion by the address conversion circuit, data is moved according to the memory control circuit, and the desired operation is completed by restoring the register settings.

′−,) [Operation] In the conventional method, data is transferred from one memory circuit with duplicate addresses to the other memory circuit. j: The moving process required two moving operations and a memory area to temporarily store the data to be moved.
Only one movement operation is required, and an area to temporarily store the data to be moved is not required, which speeds up the processing of moving data from one memory circuit with duplicate addresses to another memory circuit. can.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the components of an embodiment of the present invention. In FIG. 1, 10 is an address setting circuit;
0 is a memory control circuit, 30 is a read/write condition setting circuit, 40 is an address conversion circuit, and 50 is a memory circuit. The memory control circuit 20 includes a comparison circuit 21 and a control signal generation circuit 22. Next, the upper bits of the address to explain the working example? If they match, the control signal generation circuit 21 outputs a chip select signal to the memory circuit 5o.Also, the control signal generation circuit 21 makes sure that read permission is set in the read/write condition setting circuit 3o. If so, a memory control signal is output to the memory circuit 5o. Further, the address conversion circuit 40 converts the lower bits of the address and outputs an address signal to the memory circuit 50.

Thereafter, the memory circuit 5o outputs a data signal to the system bus to complete the read operation.

The same applies to the case where a memory write request is generated from the system bus, so the description will be omitted.

In this way, the comparison of addresses is performed by the settings of the address setting circuit 10, so by changing the settings, data can be easily moved from one address to another. In addition, read and write setting circuit 3o
By changing the setting values, read prohibition, permission, write prohibition, and permission can be freely changed. Furthermore, the address conversion circuit 4゜ has a memory chip of 64KB and 256K.
If the address capacity is larger than the data length, such as B, it is necessary to use the memory chip number effectively. for example,
The case where the memory chip has an address of 64 KB and the data length is 4 KB will be explained using the address conversion method shown in FIG. 2. In FIG. 2, the memory circuit 50 is divided into 16 blocks, and each block has an address setting circuit 10 and an address conversion circuit 40. still,
Lead for simplicity of explanation.

The write setting circuit 30 and memory control circuit 2o are omitted.

No memory access request is generated from the system bus.
The upper bits of the address and the contents of the address setting circuit 10 are compared. If the upper bits of the address match the contents of block #1 in the address setting circuit 10, the address conversion circuit 40 outputs the lower bits of the address as is as an address signal for the memory circuit 5. If the upper bit of the address is
If the contents match the contents of block #2, the address conversion circuit 40 sets (1000) to the lower bits of the address.
+6 is added and output as an address signal for the memory circuit 50. Similarly, if it matches block #5, (
2000) + 6 If it matches #4, (3000
) 1610 Tsuku #16! If it matches, (Fooo)+
In addition to the lower bit of the No. 6 address, Q is output as an address signal for the memory circuit 50. From the above explanation, when moving data from one memory circuit with a duplicate address to the other memory circuit, -
It is understood that it is sufficient to move the data once.

Next, an embodiment in which the present invention is applied to a terminal control device will be described. It is assumed that the terminal control device has the following functions.

■Video terminal input processing (α) Receive data number from the terminal in 4KB from address 'AOOOO'.

(b) Move data to address 'BOOOO'.

(C) Send data to the host at address 'B 0000'.

■Video terminal output processing (α) Receive 4KB data from the host from address 'Coooo'0 (b) Move data to address 'DOOOO'.

(C) Send data at address 'Do 000' to terminal 0 ■ Simultaneous print processing (α) Receive data from host in 4 KB from address coooo'.

(b) Same data at addresses 'D0000' and 'EO'
Move to OOO'.

(Q) Send the data at address 'DOOOO' to the video terminal.

(d) Send the data at address 'EOOOO' to the printer terminal.

■Management data accumulation processing (α) Management data is stored in 'F' at the same address as the ROM area.
Accumulate to OOOO'.

(b) During normal operation, ROM from address 'FOOOO'
The content of is read.

(Q) When outputting management data, move the management data stored at address 'FOODO' to address 'EOOOO'.

(d) Send the data at address 'EOOOO' to the printer terminal.

An example of the operation of the present invention in the above process is shown in the flowcharts of FIGS. 3 to 6.

FIG. 5 is a flowchart showing video terminal input processing. First, write the address 'AOOOOO' into the address setting circuit.
' is set (301) L, and the data signal is received there from the terminal (302). Next, address 'B' is input to the address setting circuit.
Set OOOO' (303) L, and send data from there to the host (SOa). In this way, the process of moving input data from a terminal to the host sending 1S area can be instantaneously executed by changing the contents of the address setting circuit.

FIG. 4 is a flowchart showing video terminal output processing. First, set the address 'coooo' to the address setting circuit.
' is set (401) L, and data from the host is received there (402). Next, the address 'DOOOO' is set in the address setting circuit (405), and data is sent from there to the terminal (404). In this way, by changing the contents of the address setting circuit from the host, it can be executed instantly.

Is Figure 5 a simultaneous print process? FIG. First, the address 'coooo' is set in the address setting circuit of the first memory circuit (502) L, and the read/write condition is set to write permission. Next, the address 'Coooo' is set in the address setting circuit of the second memory circuit (504) L, and the read/write condition is set to write permission. Then address the data from the host'
Coooo' is received (506). First, the address 'DOOOO' is set in the address setting circuit of the first memory circuit (508), and then the address 'EOOOO' is set in the address setting circuit of the second memory circuit (510).

Then, data is sent from each address to the terminal (51
2). In this way, by setting the two memory circuits to the same address and enabling write, it is possible to simultaneously receive output data from the host into the two memory circuits. In other words, data can be easily copied.

It's a yard. First, set the address 'F' to the address setting circuit.
OOOO' is set (602) [,, After setting the read/write condition to read prohibition, management data is accumulated there (604). Then, set the address 'EO000' in the address setting circuit (606) L, data from that address to the terminal? Send (6OS).

In this way, for data that is only stored but never read during normal operation, the memory circuit for data storage is set to R.
By setting the same address as the OM and disabling reading, it is possible to substantially expand the memory space ◇ [Effects of the Invention] As explained above, according to the present invention, memory with duplicate addresses You can reduce the time required to move data between
Also, moving data from one area to another, R
By using the same address as the OM area, the actual memory space can be expanded, and by duplicating the address, it is easy to copy data.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram for explaining an address conversion method, FIG. 3 is a flowchart showing video terminal input processing, and FIG. 4 is a video terminal output FIG. 5 is a flowchart showing the simultaneous printing process, and FIG. 6 is a flowchart showing the management data accumulation process. 10...Address setting circuit 20...Memory control circuit 30...Read and write condition setting circuit 40...Address conversion circuit 50...Memory circuit Figure 2

Claims (1)

[Claims] 1. It has a circuit for setting addresses, a circuit for setting read and write conditions, a circuit for converting addresses, a circuit for controlling memory, and a memory circuit, and the address set in the circuit for setting the address is transferred to the entire memory circuit. or the start address of a part thereof, and if necessary, after performing address conversion by a circuit that converts the address, accesses the memory circuit according to the settings of the circuit that sets the read and write conditions, A memory control method characterized in that data is then moved by rewriting the contents set in the circuit that sets the address.