JPS622251U - - Google Patents

Info

Publication number
JPS622251U
JPS622251U JP9231885U JP9231885U JPS622251U JP S622251 U JPS622251 U JP S622251U JP 9231885 U JP9231885 U JP 9231885U JP 9231885 U JP9231885 U JP 9231885U JP S622251 U JPS622251 U JP S622251U
Authority
JP
Japan
Prior art keywords
glass
fixing
ceramic
package
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9231885U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9231885U priority Critical patent/JPS622251U/ja
Publication of JPS622251U publication Critical patent/JPS622251U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図乃至第４図はこの考案の実施例の各縦断
面図であり、第５図は金属フレーム不使用の場合
の縦断面図。第６図はパツケージ本体に直接光学
ガラスを載置したものを示し、第７図はこの考案
のＩＣパツケージの斜視図。第８図は、従来のも
のを示す。 １……縁取り枠、２……光学ガラス、３……セ
ラミツクフレーム、４……シールガラス、５……
金属フレーム、６……パツケージ本体。 FIGS. 1 to 4 are longitudinal sectional views of embodiments of this invention, and FIG. 5 is a longitudinal sectional view of the case where no metal frame is used. FIG. 6 shows a case in which optical glass is placed directly on the package body, and FIG. 7 is a perspective view of the IC package of this invention. FIG. 8 shows a conventional one. 1...Edging frame, 2...Optical glass, 3...Ceramic frame, 4...Seal glass, 5...
Metal frame, 6...package body.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] セラミツクフレーム又はパツケージ本体上にシ
ールガラスを介してガラスを固定するとともに、
このガラス上にセラミツクもしくは金属よりなる
縁取り枠を固定してなるＩＣパツケージ。 While fixing the glass on the ceramic frame or package body via the seal glass,
An IC package is made by fixing a ceramic or metal edging frame onto this glass.
JP9231885U 1985-06-20 1985-06-20 Pending JPS622251U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9231885U JPS622251U (en) 1985-06-20 1985-06-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9231885U JPS622251U (en) 1985-06-20 1985-06-20

Publications (1)

Publication Number Publication Date
JPS622251U true JPS622251U (en) 1987-01-08

Family

ID=30649009

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9231885U Pending JPS622251U (en) 1985-06-20 1985-06-20

Country Status (1)

Country Link
JP (1) JPS622251U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59132147A (en) * 1983-01-19 1984-07-30 Toshiba Corp Airtight sealing method for semiconductor device
JPS59224145A (en) * 1983-06-03 1984-12-17 Hitachi Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59132147A (en) * 1983-01-19 1984-07-30 Toshiba Corp Airtight sealing method for semiconductor device
JPS59224145A (en) * 1983-06-03 1984-12-17 Hitachi Ltd Semiconductor device

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