JPS62222661A - Electronic component part with lead and manufacture thereof - Google Patents
Electronic component part with lead and manufacture thereofInfo
- Publication number
- JPS62222661A JPS62222661A JP6768386A JP6768386A JPS62222661A JP S62222661 A JPS62222661 A JP S62222661A JP 6768386 A JP6768386 A JP 6768386A JP 6768386 A JP6768386 A JP 6768386A JP S62222661 A JPS62222661 A JP S62222661A
- Authority
- JP
- Japan
- Prior art keywords
- external lead
- lead pin
- insulating base
- electronic component
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 238000005260 corrosion Methods 0.000 claims abstract description 7
- 230000007797 corrosion Effects 0.000 claims abstract description 7
- 238000003825 pressing Methods 0.000 claims description 2
- 239000011247 coating layer Substances 0.000 abstract description 17
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 abstract description 11
- 239000010410 layer Substances 0.000 abstract description 8
- 239000011248 coating agent Substances 0.000 abstract description 4
- 238000000576 coating method Methods 0.000 abstract description 4
- 239000010949 copper Substances 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 239000000919 ceramic Substances 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010931 gold Substances 0.000 description 7
- 238000002845 discoloration Methods 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000011572 manganese Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 239000012777 electrically insulating material Substances 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 229910052748 manganese Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical class [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は外部リードピンがかしめ止めにより取着されて
なる電子部品、具体的にはＩＣパッケージやハイブリッ
ドＩＣ用配線基板等のリード付き電子部品に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to electronic components having external lead pins attached by caulking, specifically electronic components with leads such as IC packages and wiring boards for hybrid ICs. It is something.
（従来の技術）
従来、リード付き電子部品、例えば半導体集積回路素子
を収納するためのＩＣパッケージは第３図に示すように
、セラミック、ガラス、樹脂等の電気絶縁材料から成り
、その上面にモリブデン（Ｍｏ）、マンガン（Ｍｎ）
、タングステン（匈）、ニッケル（Ｎｉ）、銅（Ｃｕ）
等の金属から成る金属層１２を有する絶縁基体１１と、
半導体集積回路素子を外部電気回路に電気的に接続する
ために前記金属層１２と接続され、かつ絶縁基体１１に
取着された外部リードピン１３と、椀状の蓋体１４とか
ら構成されており、その内部に半導体集積回路素子１５
が収納され、気密封止されて半導体装置となる。(Prior Art) Conventionally, as shown in FIG. 3, an IC package for accommodating an electronic component with leads, such as a semiconductor integrated circuit element, is made of an electrically insulating material such as ceramic, glass, or resin, and is coated with molybdenum on the top surface. (Mo), manganese (Mn)
, tungsten, nickel (Ni), copper (Cu)
an insulating base 11 having a metal layer 12 made of a metal such as;
It consists of an external lead pin 13 connected to the metal layer 12 and attached to the insulating base 11 in order to electrically connect the semiconductor integrated circuit element to an external electric circuit, and a bowl-shaped lid 14. , a semiconductor integrated circuit element 15 inside thereof.
is housed and hermetically sealed to form a semiconductor device.
この従来のＩＣパッケージは通常、外部リードピン１３
が絶縁基体１１に設けた貫通孔内に挿通され、しかる後
、外部リードピン１３の上部もしくは下部より圧力を印
加し、外部リードピン１３の一部を絶縁基体１１を挟持
するよう変形させる、所謂かしめ止めによって絶縁基体
１１に取着されており、外部リードピン１３と金属層１
２とはハンダ１６を介し電気的に接続されている。This conventional IC package typically has external lead pins 13
is inserted into a through hole provided in the insulating base 11, and then pressure is applied from the upper or lower part of the external lead pin 13 to deform a part of the external lead pin 13 so as to sandwich the insulating base 11, so-called caulking. It is attached to the insulating base 11 by the external lead pin 13 and the metal layer 1.
2 and is electrically connected via solder 16.
（発明が解決しようとする問題点）
しかし乍ら、この従来のＩＣパッケージは、通常外部リ
ードビン１３がかしめ止めの容易さ、導電率の高さ等か
ら銅（Ｃｕ）が使用されており、該銅は大気中の水分が
付着すると酸化され、銅（Ｃｕ）の酸化物（錆）を形成
して変色させることがある。この銅の酸化物は導電性で
、かつ拡散しやすいという性質を有しているため多数の
外部リードビンが近接してかしめ止めされている場合に
は、前記錆の拡散により隣接する外部リードピンが短絡
し、その結果、半導体装置としての機能に支障を来すと
いう重大な欠点を誘発する。(Problems to be Solved by the Invention) However, in this conventional IC package, copper (Cu) is usually used for the external lead bin 13 due to its ease of caulking and high conductivity. Copper is oxidized when atmospheric moisture adheres to it, forming copper (Cu) oxides (rust) and causing discoloration. This copper oxide is conductive and easily diffuses, so if a large number of external lead pins are caulked in close proximity, adjacent external lead pins will short-circuit due to the diffusion of the rust. However, as a result, a serious drawback arises in that the function as a semiconductor device is hindered.
また上記欠点を解消するために外部リードピン１３を絶
縁基体１１にかしめ止めした後、外部リードピン１３の
外表面をめっきにより化学的に安定な金（Ａｕ）等で被
覆することも考えられるが、めっき液の循環が悪いこと
に起因して絶縁基体１１の貫通孔内に位置する外部リー
ドピン１３の外表面を完全に被覆することができず、そ
の結果、絶縁基体１１の貫通孔内に位置する外部リード
ピン１３の外表面に大気中に含まれる水分等が付着する
と前述と同様の問題が発生してしまう。Furthermore, in order to eliminate the above-mentioned drawbacks, it is conceivable to caulk the external lead pin 13 to the insulating base 11 and then cover the outer surface of the external lead pin 13 with chemically stable gold (Au) or the like by plating. Due to poor liquid circulation, the outer surface of the external lead pin 13 located within the through hole of the insulating base 11 cannot be completely covered, and as a result, the external lead pin 13 located within the through hole of the insulating base 11 cannot be completely covered. If moisture contained in the atmosphere adheres to the outer surface of the lead pin 13, the same problem as described above will occur.
（発明の目的）
本発明者は上記欠点に鑑み種々の実験の結果、外部リー
ドピンの外表面全面を予め化学的に安定な、ビッカース
硬度（）ｌｖ）が１４０以下の金属で被覆しておき、こ
れを絶縁基体にかしめ止めすると外部リードピンに導電
性の錆の発生を皆無として、かつ絶縁基体に強固に取着
し得ることを知見した。(Object of the Invention) In view of the above-mentioned drawbacks, the present inventor has conducted various experiments and found that the entire outer surface of the external lead pin is coated in advance with a chemically stable metal having a Vickers hardness (lv) of 140 or less. It has been found that when this is caulked to an insulating base, there is no occurrence of conductive rust on the external lead pin, and it can be firmly attached to the insulating base.
本発明は上記知見に基づき、変色や電子部品としての機
能に支障を来すような導電性の錆の発生を防止し、かつ
外部リードピンを絶縁基体に強固にかしめ止めして取着
強度が極めて大のリード付き電子部品及びその製造方法
を提供することをその目的とするものである。Based on the above knowledge, the present invention prevents discoloration and the occurrence of conductive rust that may impede the function of electronic components, and also provides extremely strong mounting strength by firmly caulking external lead pins to an insulating base. The object of the present invention is to provide a large leaded electronic component and a method for manufacturing the same.
（問題点を解決するための手段）
本発明は絶縁基体に設けた貫通孔内に外部リードピンを
かしめ止めにより取着して成るリード付き電子部品にお
いて、前記外部リードピンの外表面全面をビッカース硬
度が１４０以下の耐蝕性金属で被覆したことを特徴とす
るものである。(Means for Solving the Problems) The present invention provides a leaded electronic component in which an external lead pin is attached by caulking in a through hole provided in an insulating base, and in which the entire outer surface of the external lead pin has a Vickers hardness. It is characterized by being coated with a corrosion-resistant metal of 140 or less.
本発明はＩＣパッケージ、ハイブリッドＩＣ用配線基板
等の絶縁基体に外部リードピンがかしめ止めにて取着さ
れる電子部品のすべてに適用される。The present invention is applicable to all electronic components in which external lead pins are attached by caulking to an insulating substrate such as an IC package or a wiring board for a hybrid IC.
（実施例）
次に本発明を第１図に示す実施例に基づき詳細に説明す
る。(Example) Next, the present invention will be described in detail based on an example shown in FIG.
第１図は本発明のリード付き電子部品を半導体集積回路
素子を収納するＩＣパフケージに適用した場合の一実施
例を示し、１はセラミック、ガラス、樹脂等の電気絶縁
材料から成る絶縁基体である。FIG. 1 shows an embodiment in which the leaded electronic component of the present invention is applied to an IC puff cage that houses a semiconductor integrated circuit element, and 1 is an insulating base made of an electrically insulating material such as ceramic, glass, or resin. .
前記絶縁基体ｌの上面中央部には半導体集積回路素子５
が接着材を介し取着されている。A semiconductor integrated circuit element 5 is provided at the center of the upper surface of the insulating substrate l.
is attached via adhesive.
また前記絶縁基体１の上面には金属Ｎ２が被着形成され
ており、該金属層２の一端には半導体集積回路素子５の
電極がワイヤ６を介し接続され、また他端は後述する絶
縁基体１にかしめ止めされた外部リードピン３にハンダ
７を介し接続される。Further, a metal N2 is deposited on the upper surface of the insulating base 1, and an electrode of a semiconductor integrated circuit element 5 is connected to one end of the metal layer 2 via a wire 6, and the other end is connected to the insulating base described later. It is connected via solder 7 to an external lead pin 3 which is caulked to 1.
これにより半導体集積回路素子５は外部リードピン３を
外部電気回路と接続した際、ワイヤ８．金属層２及び外
部リードピン３を介し外部電気回路と接続されることと
なる。As a result, when the semiconductor integrated circuit element 5 connects the external lead pin 3 to an external electric circuit, the wire 8. It will be connected to an external electric circuit via the metal layer 2 and external lead pins 3.
前記金属層２はモリブデン（ＨＯ）、マンガン（Ｍｎ）
、タングステン（Ｗ）、金（Ａｕ）、銅（Ｃｕ）等の金
属から成り、従来周知の厚膜手法、薄膜手法を採用する
ことにより絶縁基体１上に被着形成される。The metal layer 2 is made of molybdenum (HO) and manganese (Mn).
, tungsten (W), gold (Au), copper (Cu), etc., and is deposited on the insulating substrate 1 by employing a conventionally well-known thick film method or thin film method.
また前記金属Ｎ２の一端が接続される外部リードピン３
は絶縁基体１に設けた貫通孔ｌａ内にかしめ止めによっ
て取着されており、該外部リードピン３は半導体集積回
路素子を外部電気回路に接続する作用を為す。Also, an external lead pin 3 to which one end of the metal N2 is connected.
is attached by caulking into a through hole la provided in the insulating base 1, and the external lead pin 3 functions to connect the semiconductor integrated circuit element to an external electric circuit.
前記外部リードピン３は銅（Ｃｕ）等のかしめ止めに適
した硬度を有し、かつ導電率が高い材料から成り、その
外表面全面が金（Ａｕ）、銀（Ａｇ）、インジウム（Ｉ
ｎ） 、スズ（Ｓｎ）、鉛（Ｐｄ）等の化学的に安定で
、かつビッカース硬度が１４０以下の金属から成る被覆
層３ａによって覆われている。そのためこの外部リード
ビン３に大気中に含まれる水分等が直接付着することは
なく、外部リードビン３に錆が発生することは一切ない
。また外部リードビン３の外表面に被着した被覆層３ａ
に水分等が付着しても該被覆層３ａは化学的に安定な耐
蝕性に優れた材料であることから錆を発生することもな
い。The external lead pin 3 is made of a material having hardness suitable for caulking and high conductivity, such as copper (Cu), and its entire outer surface is made of gold (Au), silver (Ag), or indium (I).
n) is covered with a coating layer 3a made of a chemically stable metal such as tin (Sn) or lead (Pd) and having a Vickers hardness of 140 or less. Therefore, moisture contained in the atmosphere does not directly adhere to the external lead bin 3, and no rust occurs on the external lead bin 3. In addition, a coating layer 3a adhered to the outer surface of the external lead bin 3
Even if moisture or the like adheres to the coating layer 3a, rust will not occur because the coating layer 3a is made of a chemically stable material with excellent corrosion resistance.
前記外部リードビン３の外表面全面に被着された被覆層
３ａは外部リードビン３を絶縁基体１にかしめ止めする
前に外部リードビン３の外表面全面に被着され、金（Ａ
ｕ） 、銀（Ａｇ）等の金属をめっきにより、その厚み
が２．０〜１０．０μＩとなるように被着される。The coating layer 3a is coated on the entire outer surface of the external lead bin 3 before the outer lead bin 3 is caulked to the insulating base 1, and is made of gold (A).
u) A metal such as silver (Ag) is deposited by plating to a thickness of 2.0 to 10.0 μI.
また前記絶縁基体１の上面にはセラミック、ガラス、樹
脂等の電気絶縁材料から成る椀状の蓋体４がガラス、樹
脂等の封止部材を介して取着されており、これによりＩ
Ｃパッケージ内部に半４体集積回路素子５が収納され、
気密封止されて最終製品である半導体装置となる。A bowl-shaped lid 4 made of an electrically insulating material such as ceramic, glass, or resin is attached to the upper surface of the insulating base 1 via a sealing member such as glass or resin.
A semi-quad integrated circuit element 5 is housed inside the C package,
It is hermetically sealed to become the final product, a semiconductor device.
次に本発明のリード付き電子部品における絶縁基体に外
部リードビンを取着する方法について第２図に示す工程
図に基づき説明する。Next, a method for attaching an external lead bin to an insulating substrate in a leaded electronic component of the present invention will be explained based on the process diagram shown in FIG.
まず第２図（ａ）に示す如く、中間部に鍔部３ｂを有し
、外表面全面に被覆層３ａを有する外部リードビン３を
治具Ａの貫通孔に鍔部３ｂを治具Ａ上面に係止させて装
填する。First, as shown in FIG. 2(a), an external lead bin 3 having a flange 3b in the middle and a coating layer 3a on the entire outer surface is inserted into the through hole of jig A, and the flange 3b is attached to the upper surface of jig A. Lock and load.
次に第２図（ｂ）に示す如く、治具Ａに装填した外部リ
ードビン３を上面に金属層２を有する絶縁基体ｌの貫通
孔ｌａ内に挿通させる。この場合、絶縁基体１の貫通孔
１ａはその孔径が外表面に被覆層３ａを有する外部リー
ドビン３の外径と同一もしくはそれより若干大となして
あり、貫通孔１ａ内へのり−ドピン３の挿通を容易とな
しである。Next, as shown in FIG. 2(b), the external lead bin 3 loaded in the jig A is inserted into the through hole la of the insulating base l having the metal layer 2 on the upper surface. In this case, the diameter of the through hole 1a of the insulating base 1 is the same as or slightly larger than the outer diameter of the external lead bin 3 having the coating layer 3a on the outer surface, and the pin 3 is inserted into the through hole 1a. Easy and no insertion.
尚、前記貫通孔１ａは絶縁基体１がセラミックから成る
場合には、焼成前のセラミックグリーンシートに従来周
知の打抜き加工法により穿孔しておくことによって形成
され、また樹脂から成る場合には、硬化板状体となした
ものに従来周知の孔あけ加工法により穿孔することによ
って形成される。In addition, when the insulating substrate 1 is made of ceramic, the through hole 1a is formed by punching a ceramic green sheet before firing using a conventionally known punching method, and when it is made of resin, it is formed by punching the ceramic green sheet before firing. It is formed by drilling holes in a plate-shaped body using a conventionally well-known drilling method.
そして最後に第２図（ｃ）に示す如く、外部り一ドピン
３の頭部を圧力印加装置Ｂにより５０Ｋｇ／ｃｍ”の圧
力で押圧し、外部リードビン３の頭部を変形させて鍔部
３Ｃを形成し、該鍔部３Ｃと３ｂとで絶縁基体１を挟持
させることによって外部リードビン３の絶縁基体１への
かしめ止めによる取着が完了する。Finally, as shown in FIG. 2(c), the head of the external lead pin 3 is pressed with a pressure of 50 kg/cm'' by the pressure applying device B, and the head of the external lead pin 3 is deformed and the flange 3C is pressed. By forming and sandwiching the insulating base 1 between the flanges 3C and 3b, attachment of the external lead bin 3 to the insulating base 1 by caulking is completed.
尚、この場合、外部リードビン３の外表面全面に被着さ
れている被覆１ｔｉ３ａはそのビッカース硬度（Ｈｖ）
が１４０以下であり、軟質であることから外部リードビ
ン３の頭部を圧力印加装置Ｂにより押圧、変形させる際
、外部リードビン３に追従して同様の変形を行い外部リ
ードビン３の外表面から剥離したり、あるいは被覆Ｎ３
ａ中にクランクが発生したりすることはなく、かしめ止
め後も外部リードビン３の外表面全面を完全に被覆する
ことができる。In this case, the coating 1ti3a applied to the entire outer surface of the external lead bin 3 has a Vickers hardness (Hv) of
is 140 or less and is soft, so when the head of the external lead bin 3 is pressed and deformed by the pressure application device B, it follows the external lead bin 3 and deforms in the same way, and peels off from the outer surface of the external lead bin 3. or coating N3
There is no occurrence of cranking during the process (a), and the entire outer surface of the external lead bin 3 can be completely covered even after caulking.
また被覆層３ａはそのビッカース硬度（Ｈｖ）を９０以
下としておくと外部リードビンを押圧、変形させてかし
め止めする際、その押圧速度を極めて速くなしても被覆
層３ａが外部リードビン３より剥離したり、クランクが
発生したりすることはなく、量産性の点で被覆Ｎ３ａは
ビッカース硬度を９０以下としておくことが好ましい。Furthermore, if the Vickers hardness (Hv) of the coating layer 3a is set to 90 or less, when the external lead bin is pressed, deformed, and caulked, the coating layer 3a may peel off from the external lead bin 3 even if the pressing speed is extremely high. From the viewpoint of mass production, it is preferable that the Vickers hardness of the coating N3a is 90 or less so that no cranking occurs.
（実験例）
次に本発明の作用効果を下記に示す実験例に基づいて説
明する。(Experimental Example) Next, the effects of the present invention will be explained based on the experimental example shown below.
まず、銅（Ｃｕ）から成る直径０．５ ｍｍφの外部リ
ードビンを準備するとともにその外表面全面にめっきに
より第１表に示す各種金属の被覆層を被着させて試料を
得る。First, an external lead bottle made of copper (Cu) with a diameter of 0.5 mm is prepared, and a coating layer of various metals shown in Table 1 is coated on the entire outer surface by plating to obtain a sample.
次に各試料２０個づつをセラミック焼結体に設けた直径
０．７ ｍｍφの貫通孔内に挿通させ、しかる後第２図
に示す方法によって５０Ｋｇ／ｃｍ”の圧力で押圧し、
変形させてかしめ止めをする。Next, 20 of each sample were inserted into a through hole with a diameter of 0.7 mm in the ceramic sintered body, and then pressed with a pressure of 50 kg/cm'' by the method shown in Fig. 2.
Deform it and caulk it.
次に、これらをＭＩＬ−３ＴＤ−８８３−１００４に規
定の温湿度サイクル試験を２４０時間（１０サイクル）
行い、その後、外部リードビンの表面を顕微鏡により観
察し、変色しているものの数を調べた。Next, these were subjected to a temperature/humidity cycle test specified in MIL-3TD-883-1004 for 240 hours (10 cycles).
After that, the surface of the external lead bin was observed under a microscope to determine the number of discolored ones.
尚、試料番号９及び１０は本発明品と比較するための比
較試料であり、試料番号９は外部リードピンの外表面に
被覆層を全く被着してないもの、また試料番号１０はか
しめ止め後、外部リードピンの外表面にめっきにより被
覆層を被着したものである。Sample numbers 9 and 10 are comparative samples for comparison with the products of the present invention. Sample number 9 has no coating layer applied to the outer surface of the external lead pin, and sample number 10 has no coating layer applied to the outer surface of the external lead pin, and sample number 10 is the one after caulking. , a coating layer is applied to the outer surface of the external lead pin by plating.
上記の結果を第１表に示す。The above results are shown in Table 1.
第１表
本印を付した試料番号のものは本発明の範囲外のもので
ある。Sample numbers marked in Table 1 are outside the scope of the present invention.
（発明の効果）
上記実験結果からも判るように銅から成る外部リードピ
ンをそのまま絶縁基体（セラミック焼結体）にかしめ止
めしたものは錆の発生による変色率が９５％もあり、ま
たかしめ止め後の外部リードピンに被覆層を設けたもの
は絶縁基体の貫通孔内部より錆が発生し、その変色率が
８０χもあるのに対し、本発明の外表面全面に予めビッ
カース硬度（Ｈｖ）が１４０以下の耐蝕性金属から成る
被覆層を被着した外部リードピンをかしめ止めしたもの
は錆の発生による変色は全く発生していない。(Effects of the invention) As can be seen from the above experimental results, when the external lead pin made of copper is caulked directly to the insulating base (ceramic sintered body), the rate of discoloration due to rust is as high as 95%. In the case where a coating layer is provided on the external lead pin of the invention, rust occurs from inside the through hole of the insulating base, and the discoloration rate is as high as 80χ. The external lead pins covered with a coating layer made of a corrosion-resistant metal are caulked, and no discoloration due to rust occurs at all.
従って、外表面全面にピンカース硬度が１４０以下の耐
蝕性金属から成る被覆層を有する外部リードビンをかし
め止めにより取着した本発明のリード付き電子部品は変
色や電子部品としての機能に支障を来すような導電性の
錆の発生が有効に防止され、信頼性を掻めて高いものと
なすことができる。Therefore, the leaded electronic component of the present invention, in which an external lead bin having a coating layer made of a corrosion-resistant metal with a Pinkers hardness of 140 or less is attached to the entire outer surface by caulking, may discolor or impede its function as an electronic component. The occurrence of such conductive rust is effectively prevented, and reliability can be improved.
第１図は本発明のリード付き電子部品としてＩＣパッケ
ージを例とした場合の断面図、第２図（ａ）〜（ｃ）は
第１図のＩＣパッケージにおける外部り−ドピンを絶縁
基体に取着する際の取着方法を説明するための工程図、
第３図は従来のリード付き電子部品としてＩＣパッケー
ジを例とした断面図である。
１：絶縁基体 １ａ：貫通孔FIG. 1 is a cross-sectional view of an IC package as an example of the leaded electronic component of the present invention, and FIGS. 2(a) to (c) show how the external lead pins of the IC package shown in FIG. 1 are attached to an insulating base. A process diagram to explain how to attach the
FIG. 3 is a cross-sectional view of an IC package as an example of a conventional electronic component with leads. 1: Insulating base 1a: Through hole
Claims (2)
しめ止めにより取着して成るリード付き電子部品におい
て、前記外部リードピンの外表面全面をビッカース硬度
が１４０以下の耐蝕性金属で被覆したことを特徴とする
リード付き電子部品。(1) In a lead-equipped electronic component in which an external lead pin is attached by caulking into a through hole provided in an insulating base, the entire outer surface of the external lead pin is coated with a corrosion-resistant metal having a Vickers hardness of 140 or less. An electronic component with leads featuring the following.
ース硬度１４０以下の耐蝕性金属で被覆された外部リー
ドピンを挿通させ、しかる後、前記外部リードピンの上
部もしくは下部より圧力を印加し、外部リードピンの一
部を絶縁基体を挟持するよう変形させることによって外
部リードピンを絶縁基体の貫通孔内に取着して成るリー
ド付き電子部品の製造方法。(2) inserting an external lead pin whose entire outer surface is coated with a corrosion-resistant metal with a Vickers hardness of 140 or less into a through hole provided in the insulating base, and then applying pressure from the top or bottom of the external lead pin; A method of manufacturing an electronic component with a lead, comprising attaching an external lead pin into a through hole of an insulating base by deforming a part of the external lead pin so as to sandwich the insulating base.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6768386A JPS62222661A (en) | 1986-03-25 | 1986-03-25 | Electronic component part with lead and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6768386A JPS62222661A (en) | 1986-03-25 | 1986-03-25 | Electronic component part with lead and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62222661A true JPS62222661A (en) | 1987-09-30 |
Family
ID=13352035
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6768386A Pending JPS62222661A (en) | 1986-03-25 | 1986-03-25 | Electronic component part with lead and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62222661A (en) |
-
1986
- 1986-03-25 JP JP6768386A patent/JPS62222661A/en active Pending
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