JPH0235762A - Terminal pin for semiconductor package - Google Patents
Terminal pin for semiconductor packageInfo
- Publication number
- JPH0235762A JPH0235762A JP18580488A JP18580488A JPH0235762A JP H0235762 A JPH0235762 A JP H0235762A JP 18580488 A JP18580488 A JP 18580488A JP 18580488 A JP18580488 A JP 18580488A JP H0235762 A JPH0235762 A JP H0235762A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- plating
- pin body
- pin
- terminal pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 229910000679 solder Inorganic materials 0.000 claims abstract description 55
- 238000007747 plating Methods 0.000 claims abstract description 38
- 229910000906 Bronze Inorganic materials 0.000 claims abstract description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000010974 bronze Substances 0.000 claims abstract description 11
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000011248 coating agent Substances 0.000 abstract description 4
- 238000000576 coating method Methods 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 5
- 239000004859 Copal Substances 0.000 description 2
- 241000782205 Guibourtia conjugata Species 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
本発明は、ビングリッドアレイなど半導体パッケージに
用いられる端子ビンに関するものである。The present invention relates to terminal bins used in semiconductor packages such as bin grid arrays.
ビングリッドアレイなどＩＣチップ等の半導体チップ７
を搭載した半導体パッケージは第２図に示すように形成
されている。すなわち、樹脂積層板などの電気絶縁性を
有する基板８の上面の中央にキャビティ用凹所９を形成
すると共に基板８の上面にキャビティ用凹所９を中心と
した放射状に回路（図示省略）を形成し、基板８に形成
したスルーホール１０．１０・・・に各回路と電気的に
接続されたスルーホールメッキを施し、スルーホール１
０に端子ビンＡの基部を挿入して端子ピン八を基板８の
下面に突出させ、そしてキャビティ用凹所９に半導体チ
ップ７を実装すると共に半導体チップ７と各回路とをボ
ンディングすることによって、基板８の上面に形成した
回路を介して半導体チップ７を各端子ビンＡに電気的に
接続させるようにして作成される。さらに基板８の上面
に封止樹脂を注入して半導体チップ７を封止して仕上げ
られる。
そしてこのように形成される半導体パッケージは、端子
ビンＡの先部をマザーボード１１などのスルーホールや
プラグ等に差し込んで半田付けすることによって、取り
付けがおこなわれるものである。Semiconductor chips such as IC chips such as bin grid arrays 7
The semiconductor package mounted with this is formed as shown in FIG. That is, a cavity recess 9 is formed in the center of the upper surface of a substrate 8 having electrical insulation properties such as a resin laminate, and circuits (not shown) are formed radially on the upper surface of the substrate 8 around the cavity recess 9. Through-hole plating is applied to the through-holes 10, 10, . . . , which are electrically connected to each circuit.
By inserting the base of the terminal pin A into 0 and making the terminal pin 8 protrude from the bottom surface of the substrate 8, and mounting the semiconductor chip 7 in the cavity recess 9, and bonding the semiconductor chip 7 and each circuit, The semiconductor chip 7 is manufactured by electrically connecting the semiconductor chip 7 to each terminal bin A through a circuit formed on the upper surface of the substrate 8. Further, a sealing resin is injected into the upper surface of the substrate 8 to seal the semiconductor chip 7 and finish the process. The semiconductor package formed in this manner is attached by inserting the tip of the terminal pin A into a through hole, plug, etc. of the motherboard 11 and soldering.
しかしこのものにあって、端子ピンＡの母材金属が酸化
されると半田に対する濡れが悪くなり、マザーボード１
１に対する端子ピンＡの半田付は不良が発生するおそれ
がある。このために端子ピンへの表面を半田メッキで被
覆するなどして端子ピンＡの酸化を防止する試みがなさ
れているが、高温高湿下で保管されるなど端子ピンＡに
高温高湿が作用すると、端子ピンＡに酸化が発生するこ
とを防止することができず、半田濡れ性が低下してしま
うものであった。
本発明は上記の点に鑑みて為されたものであり、高温高
湿が作用しても酸化されることを防止することができる
半導体パッケージ用端子ビンを提供することを目的とす
るものである。However, in this case, if the base metal of terminal pin A is oxidized, wetting with solder becomes poor, and the motherboard
There is a risk that a defect may occur when the terminal pin A is soldered to the terminal pin A. For this reason, attempts have been made to prevent terminal pin A from oxidizing by coating the surface of the terminal pin with solder plating, etc.; As a result, it was not possible to prevent the terminal pin A from being oxidized, resulting in a decrease in solder wettability. The present invention has been made in view of the above points, and it is an object of the present invention to provide a terminal bin for a semiconductor package that can be prevented from being oxidized even under high temperature and high humidity. .
本発明に係る半導体パッケージの端子ピンは、ピン本体
１をリン青銅で形成し、ピン本体１の表面にＮｉメッキ
２を施すと共にＮｉメッキ２の表面を半田で被覆して半
田メッキ３を施し、ビン本体１の少なくとも先端部の半
田メッキ３をＳｎ含有率が８０重量％以下の半田で形成
して成ることを特徴とするものである。In the terminal pin of the semiconductor package according to the present invention, the pin body 1 is formed of phosphor bronze, the surface of the pin body 1 is coated with Ni plating 2, the surface of the Ni plating 2 is coated with solder, and solder plating 3 is applied, The bottle body 1 is characterized in that the solder plating 3 on at least the tip thereof is formed of solder having an Sn content of 80% by weight or less.
本発明にあっては、端子ピンＡをこのように形成するこ
とによって、高温高湿の状態下においてもビン本体１（
特にその先端部）に酸化が発生することを防止すること
ができる。In the present invention, by forming the terminal pin A in this manner, the bottle body 1 (
Oxidation can be prevented from occurring, especially at the tip.
以下本発明を実施例によって詳述する。
端子ピンＡはその上部に鍔１２を設けて円柱状に形成さ
れるものであり、その母材となるビン本体１はリン青銅
によって形成しである。ビン本体１を構成する金属とし
てはコバール（７ヱルニコ）等も用いられるが、本発明
においてはリン青銅を用いることに限定される。そして
ビン本体１の全表面にＮｉメッキ２を下地メッキとして
施すと共にさらにＮｉメッキ２の全表面に半田を被覆し
て半田／ツキ３を施すことによって端子ピンＡを形成す
るものである。下地メッキとしてはＣｕメ７キなどを用
いることも可能であるが、本発明ではＮｉメッキ２に限
定される。また、半田メッキ３を構成する半田としては
、Ｓｎ含有率が８０重量％以下のものを用いるものであ
る。半田はＳｎとＰｂあるいはこれらにさらに微量の金
属を含む合金で、あり、Ｓｎ含有率を８０重量％に設定
することによってｐｂ含有率は２０重量％程度以上にな
る。
このようにピン本体１の材質をリン青銅に形成し、ピン
本体１施したＮｉメッキ２の上に半田メッキ３を施し、
そして半田メッキ３の半田としてＳｎ含有率が８０重量
％以下のものを用いることによって、高温高温が作用し
てもピン本体１の金属に酸化が生じることを防止するこ
とができるのである。そしてピン本体１に施す半田メッ
キ３の総てをＳｎ含有率が８０重量％以下の半田で形成
することが望ましいが、ピン本体１の金属が酸化される
ことを防止して半田の濡れ性が低下することを防ぐ必要
が特にあるのは、マザーボード１１に差し込んで半田付
けする先端部であるので、ピン本体１の先端部（先端か
ら１輪ｍ程度以上の範囲）のみにおいて半田メツ４３の
半田をＳｎ含有率が８０重量％以下の半田で形成し、他
の部分の半田はＳｎ含有率が８０重量％以上の半田で形
成するようにしてもよい。
次に本発明を実施例によって例証する。
Ｋ巖■１工影
ビン本体１をリン青銅で形成し、ピン本体１の表面に下
地メッキとして厚み５μｍのＮｉメッキ２を施すと共に
この表面にさらに厚み１μ輪の半田メッキ３を施して端
子ピンＡを作成した。このとき、半田メッキ３の半田と
しては第１表に示すＳ１１の含有率（残部はｐｂ）のも
のを用いた。
このようにして得た端子ピンＡを１００℃のスチームを
満たした容器中に８時間放置するスチームエーノング処
理し、そしてこの端子ピンＡの先部を２８０℃の半田浴
に４秒間浸漬する試験をおこない、端子ピンＡの先部の
半田の濡れの状態を目視で観察した。結果を第１表に示
す。第１表において半田濡れ性の良好なものを「○」、
少し悪いものを「Δ」、悪いものを「×」で表示した。
塩１１［Ｌ
半田メッキ３の半田としてｖＪ１表に示すＳｎの含有率
のものを用いるようにした他は、上記「実施例１，２」
と同様にした。
ル虜」「影二」−
下地メッキとしてＮｉメッキ２のかわりに厚み５μ■の
Ｃｕメッキを施すようにし、さらに半田メッキ３の半田
として第１表に示すＳｎの含有率のものを用いるように
した他は、上記［実施例１，２Ｊと同様にした。
ルＪｌ影二ｊ−
ピン本体１としてコパールで形成したものを用い、さら
に半田メツ斗３の半田として第２表に示すＳｎの含有率
のものを用いるようにした他は、上記「実施例１．２」
と同様にした。
ル玉１ニュ」−
ピン本体１としてコパールで形成したものを用い、下地
メッキとしてＮｉメッキ２のかわりに厚み５μｌのＣｕ
メッキを施すようにし、さらに半田メッキ３の半田とし
て第２表に示すＳｎの含有率のちのを用いるようにした
他は、
上記［実施例１゜
第
第
表
表
ｔＪＳ１表及１第２表の結果にみちれるように、ピン本
体１をリン青銅で形成し、ピン本体１の表面にＮｉメッ
キ２を施し、Ｎｉメッキ２の表面に半田／ツキ３を施し
、半田メッキ３をＳｎ含有率が８０重量％以下の半田で
形成することによって１土しめて、ピン本体１の酸化を
防止して半田濡れ性の低下を防ぐことができることが確
認される。
【発明の効果１
上述のように本発明にあっては、ピン本体をリン青銅で
形成し、ピン本体の表面にＮｉメッキを施すと共にＮｉ
メッキの表面を半田で被覆し、ピン本体の少なくとも先
端部を被覆する半田をＳｎ含有率が８０重量％以下の半
田で形成するようにしたので、高温高湿の状態下におい
てもピン本体に酸化が発生することを防止することがで
き、半田濡れ性が低下することを防ぐことができるもの
である。The present invention will be explained in detail below with reference to Examples. The terminal pin A is formed into a cylindrical shape with a collar 12 provided on its upper part, and the bottle body 1 serving as its base material is made of phosphor bronze. As the metal constituting the bottle body 1, Kovar (7ernico) or the like may also be used, but in the present invention, the use is limited to phosphor bronze. Then, the terminal pin A is formed by applying Ni plating 2 as a base plating to the entire surface of the bottle body 1, and further coating the entire surface of the Ni plating 2 with solder and applying solder/plying 3. Although it is possible to use Cu plating 7 or the like as the base plating, the present invention is limited to Ni plating 2. Further, as the solder constituting the solder plating 3, one having an Sn content of 80% by weight or less is used. Solder is Sn and Pb, or an alloy containing these and a trace amount of metal, and by setting the Sn content to 80% by weight, the Pb content becomes about 20% by weight or more. In this way, the material of the pin body 1 is made of phosphor bronze, and the solder plating 3 is applied on the Ni plating 2 applied to the pin body 1.
By using a solder with an Sn content of 80% by weight or less as the solder plating 3, it is possible to prevent the metal of the pin body 1 from oxidizing even when exposed to high temperatures. It is desirable that all the solder plating 3 applied to the pin body 1 be formed of solder with an Sn content of 80% by weight or less, but this prevents the metal of the pin body 1 from being oxidized and improves the wettability of the solder. It is especially necessary to prevent the soldering of the solder socket 43 only at the tip of the pin body 1 (within a range of about 1 wheel m or more from the tip), since it is especially necessary to prevent the tip from being inserted into the motherboard 11 and soldered. may be formed of solder having an Sn content of 80% by weight or less, and the solder of other parts may be formed of solder having a Sn content of 80% by weight or more. The invention will now be illustrated by examples. The main body 1 of the pin body 1 is made of phosphor bronze, and the surface of the pin body 1 is coated with Ni plating 2 with a thickness of 5 μm as a base plating, and this surface is further coated with solder plating 3 with a thickness of 1 μm to form the terminal pin. I created A. At this time, as the solder for solder plating 3, the content of S11 shown in Table 1 (the remainder was PB) was used. The terminal pin A obtained in this way is subjected to a steam treatment by leaving it in a container filled with steam at 100°C for 8 hours, and then the tip of this terminal pin A is immersed in a solder bath at 280°C for 4 seconds. A test was conducted, and the wetting state of the solder at the tip of terminal pin A was visually observed. The results are shown in Table 1. In Table 1, those with good solder wettability are marked "○",
Slightly worse results are indicated by "Δ" and worse ones are indicated by "×". Salt 11 [L Solder plating 3 solder with Sn content shown in table vJ1 was used, except that the above "Examples 1 and 2" were used.
I did the same thing. ``Le Powder'' and ``Kageji'' - Instead of Ni plating 2, Cu plating with a thickness of 5 μm was applied as the base plating, and the Sn content shown in Table 1 was used as the solder for solder plating 3. Other than that, the procedure was the same as in Examples 1 and 2J above. Example 1 except that the pin body 1 was made of copal and the solder of the solder plate 3 had the Sn content shown in Table 2. .2”
I did the same thing. - The pin body 1 is made of copal, and the base plating is Cu with a thickness of 5 μl instead of Ni plating 2.
The above [Example 1゜Table tJS1 Table 1 and Table 1 Table 2] were used for solder plating 3, and the Sn content shown in Table 2 was used as the solder for solder plating 3. As shown in the results, the pin body 1 is made of phosphor bronze, the surface of the pin body 1 is coated with Ni plating 2, the surface of the Ni plating 2 is coated with solder/stack 3, and the solder plating 3 is made of phosphor bronze. It is confirmed that by forming the pin body 1 with 80% by weight or less of solder, it is possible to prevent oxidation of the pin body 1 and prevent a decrease in solder wettability. Effect of the invention 1 As described above, in the present invention, the pin body is formed of phosphor bronze, and the surface of the pin body is plated with Ni.
The surface of the plating is coated with solder, and the solder covering at least the tip of the pin body is made of solder with an Sn content of 80% by weight or less, so the pin body will not oxidize even under high temperature and high humidity conditions. It is possible to prevent this from occurring, and it is possible to prevent a decrease in solder wettability.
第１図は本発明に係ろ端子ピンの一部の拡大断面図、第
２図は端子ビンを用いた半、゛導体パフケーノの断面図
である。
１はピン本体、
２はＮｉメッキ、
３は半田メツ
キである。FIG. 1 is an enlarged cross-sectional view of a portion of a terminal pin according to the present invention, and FIG. 2 is a cross-sectional view of a half-conductor plug using a terminal pin. 1 is the pin body, 2 is Ni plating, and 3 is solder plating.
Claims (1)
Ｎｉメッキを施すと共にＮｉメッキの表面を半田で被覆
し、ピン本体の少なくとも先端部を被覆する半田をＳｎ
含有率が８０重量％以下の半田で形成して成ることを特
徴とする半導体パッケージの端子ピン。(1) The pin body is made of phosphor bronze, the surface of the pin body is plated with Ni, the surface of the Ni plating is coated with solder, and the solder covering at least the tip of the pin body is Sn.
A terminal pin for a semiconductor package, characterized in that it is formed of solder having a content of 80% by weight or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63185804A JP2674788B2 (en) | 1988-07-26 | 1988-07-26 | Semiconductor package terminal pins |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63185804A JP2674788B2 (en) | 1988-07-26 | 1988-07-26 | Semiconductor package terminal pins |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0235762A true JPH0235762A (en) | 1990-02-06 |
| JP2674788B2 JP2674788B2 (en) | 1997-11-12 |
Family
ID=16177179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63185804A Expired - Lifetime JP2674788B2 (en) | 1988-07-26 | 1988-07-26 | Semiconductor package terminal pins |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2674788B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5508562A (en) * | 1992-12-08 | 1996-04-16 | Murata Manufacturing Co., Ltd. | Outer electrode structure for a chip type electronic part appropriate for reflow soldering |
| US6528873B1 (en) * | 1996-01-16 | 2003-03-04 | Texas Instruments Incorporated | Ball grid assembly with solder columns |
| US8864536B2 (en) | 2012-05-03 | 2014-10-21 | International Business Machines Corporation | Implementing hybrid molded solder-embedded pin contacts and connectors |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5875861A (en) * | 1981-10-30 | 1983-05-07 | Fuji Denka:Kk | Lead wire for circuit element hermetically sealing package and manufacture thereof |
-
1988
- 1988-07-26 JP JP63185804A patent/JP2674788B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5875861A (en) * | 1981-10-30 | 1983-05-07 | Fuji Denka:Kk | Lead wire for circuit element hermetically sealing package and manufacture thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5508562A (en) * | 1992-12-08 | 1996-04-16 | Murata Manufacturing Co., Ltd. | Outer electrode structure for a chip type electronic part appropriate for reflow soldering |
| US6528873B1 (en) * | 1996-01-16 | 2003-03-04 | Texas Instruments Incorporated | Ball grid assembly with solder columns |
| US8864536B2 (en) | 2012-05-03 | 2014-10-21 | International Business Machines Corporation | Implementing hybrid molded solder-embedded pin contacts and connectors |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2674788B2 (en) | 1997-11-12 |
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