JPS62221018A - Analog data processor - Google Patents

Abstract

PURPOSE:To process the analog data at a high speed and with high accuracy without applying the load to a host CPU by providing the signal input parts, a correction data producing part, an adder and a multiplier. CONSTITUTION:The corrected data is obtained just by an analog data processing part including signal input parts 61-6n and a data processing part 25. Therefore the load of a host CPU 81 is reduced. Then a correction circuit 23 which is used to obtain the corrected data can perform an operation faster than that carried out by software because the hardware operation is performed by an adder 21 and a multiplier 22. Furthermore a microprocessor 24 replaces the correction data in a fixed cycle. Thus the highly accurate corrected data is obtained even though the operational amplifiers 2 of the parts 61-6n have variation of their offset levels or gains owing to the temperature change or the change with time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an analog data processing device that processes analog data taken in from various sensors and the like.

(Prior Art) A conventional analog data processing system is shown in FIG. In the figure, 106 indicates an analog data processing device, and 107 indicates a CPU on the host side. The processing results of the analog data processing device 106 are sent to the CPU 107.

A scanning circuit 101 consisting of a semiconductor switch, a transformer, etc. is provided in the analog data processing unit 106 . The output signal of the scanning circuit 101 is sent to the operational amplifier 102, where it is amplified with a required gain. The output signal of the operational amplifier 102 is sampled and
The hold amplifier 103 samples and holds the signal. The output signal of the sampling and hold amplifier 103 is A/
It is digitized by the D converter 104 and then sent to the control circuit 105.
sent to. The control circuit 105 centrally controls the entire analog data processing device 106, and also controls the CPU
It has an interface function between 107 and 107. On the other hand, an operational amplifier 10 is connected to the input part of the scanning circuit 101.
The reference voltage source (its output is ○V) corresponds to each gain of 2.
1. ..., ○Vn" REFl-..., VREF
n) is connected, and the signal source to be measured (a sensor for obtaining an analog signal, etc.) whose output is A1°A2.
..., Ao> are connected.

In such an analog data processing system, the switch of the scanning circuit 101 is switched under the control of the control circuit 105, and the required reference voltage and analog signal of the signal source to be measured are captured. The captured signal is then subjected to Δ/D conversion and sent to the CPU 107 as it is. For this reason, CPU
107 had to perform correction processing for errors in offset and gain of the operational amplifier 102 with respect to the received digital data. Therefore, the host's CP
There is a drawback that the load is placed on the U 107 and the host CPU 107 cannot perform other processing. In addition, since the errors in Offcella 1~ and the gains mentioned above vary over time, it is necessary for the CP tJ 107 to create correction data that becomes the basis for correction every time data is input, and if this is neglected, However, the drawback was that accurate data could not be obtained.

(Problems to be solved by the invention) As described above, according to the conventional analog data processing device,
In order to finally obtain accurate data, the host C
The PU must perform a lot of calculation processing, and the host CPU
The problem rarely arises that the load on U becomes extremely large.

The present invention was made to solve these problems, and its purpose is to process analog data at high speed and with high accuracy without placing a load on the host CPU, and to allow the host CPU to obtain the desired data. An object of the present invention is to provide an analog data processing device that can be obtained.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes a signal input section that includes an amplifier that amplifies an input signal, takes in a reference signal and a signal to be measured, amplifies them, digitizes them, and outputs them; a correction data creation section that creates offset correction data and gain correction data based on the digital data of the reference signal given from this signal input section; and a correction data creation section that stores the data created by this correction data creation section. an adder that extracts and adds corresponding offset correction data from the correction data to the digital data of the signal to be measured supplied from the signal input section; The analog data processing device is constructed by including a multiplier that extracts the digital data of the signal to be measured and the corresponding gain correction data from the correction data storage section and multiplies the same, thereby quickly achieving the above object.

(Function) According to the above configuration, the correction data storage section includes:
Since the data for offset and gain correction is stored, it is possible to correct the digital data of the signal to be measured using this analog data processing device. It is fast because it is executed by software. Furthermore, the cycle for creating the correction data can be shortened or long, and the shorter it is, the higher the precision of the corrected digital data of the measurement object becomes.

(Embodiment) FIG. 1 is a block diagram of an embodiment of the present invention. In the same figure, 61.62. . . , 6o indicates a signal input section that takes in an analog signal, digitizes it, and outputs it.

These signal input sections 61, 62.

. . , 6n are connected to the data processing section 25 via a data bus 7, an address bus 8, and a control bus 9. Processing result data by the data processing unit 25 is sent to the host CPU 81 via the interface 71.

Since the signal input units 61, 62, . . . , 6° have similar configurations, the explanation for the signal input unit 61 will replace other explanations. Reference numeral 1 indicates a scanning circuit composed of semiconductor switches and the like. The scanning circuit 1 opens and opens the switches in a time-division manner, and outputs the reference signals ○V and VREF.
Output voltage A1 of the sensor, etc., which is the voltage of the voltage and the signal to be measured
．． A2, . . . , A8 are sequentially sent to the operational amplifier 2. The operational amplifier 2 amplifies the signal with a preset gain, and the gain of the operational amplifier 2 for each signal input section is responsible. The signal amplified by the operational amplifier 2 is temporarily held by the sampling and hold amplifier 3. The signal held here is digitized by the A/D converter 4, and this digital data is sent to the data processing unit 2 via the interface 51 in the control circuit 5.
5. The control circuit 5 controls the timing of opening the switch of the scanning circuit 1, the operation timing of the sampling/hold amplifier 3 and the A/D converter 4,
Sending and receiving control signals via the control bus 9;
It performs control such as sending address data to the address bus 8 and sending data from the interface 51 to the data bus 7.

Next, the configuration of the data processing section 25 will be explained. 24 indicates a microprocessor that controls the entire data processing section 25. 10 is each signal input section 61, 62, . . . , 6
11 shows a signal input section control circuit for controlling n, and 11 shows a timer. When the signal input section control circuit 10 receives the activation signal from the microprocessor 24, it activates the timer 11 and outputs data (address data) specifying a desired signal input section.

The activated timer 11, as shown in FIG. 2,
The operation start signal is sent at a predetermined period (several m5ec) T. This operation start signal is received by the signal input section designated by the data output by the signal input section control circuit 10 described above.

12 indicates an address decoder. The address decoder 12 decodes address data output from the signal input sections 61, 62, . RAM
18 includes correction data for correcting the offset and gain of the operational amplifier 2, and each signal input section 61, 62, .
. . , 6o, as shown in FIG. 3. In FIG. 3, ADCGl, ADCG2.・, ADCGn is
Input signal sections 61, 62, . . . 6□ gain correction data are shown, respectively, and ADCOI, ADCO2゜, . .
, ADCOn are input signal sections 61, 62, . . .
・, 6o offset correction data is shown. This RAM
18 is also accessed by microprocessor 24. The offset correction data read out by the address data of the address decoder 12 is set in the register 19, and the gain correction data is set in the register 20. The output of the register 19 is applied to one input terminal of the adder 21, and the data from each signal input section is applied to the other input terminal of the adder 21 via the data bus 7. That is, adder 21
Then, the data of the signal to be measured outputted from the signal input section and the offset correction data corresponding to the signal input section that outputted this data are added, and the offset is removed. The output of the adder 21 is applied to one input terminal of a multiplier 22, and the other side of the multiplier 22 is provided with a register 20.
Gain correction data is given. Multiplier 22
Then, the offset-corrected data is multiplied by the gain correction data to perform gain correction. , 17 indicates a RAM, and this RAM 17 is connected to the signal input section 61.6.
2,..., 6o to store the data of the reference signal as it is (raw data),
．． 62, ..., 6o, the data of the measurement target signal is corrected by the correction circuit 23 (
corrected data) is used for storage. In this case, address data is given from the register 16 to the address terminal A of the RAM 17, but if the data in the most significant bit part of that register is O, the area of corrected data is specified, and the most significant bit part If the data in is 1, the raw data area is specified. RAM specified in this way and in which corrected data and raw data are stored
17 memory maps are shown in FIG. In the same figure, ADCi (i=1 to n> is the signal input section 6
1 shows a data storage area corresponding to number 1. Also, the stored tail data is OV, VREF, Al, A2
, . . . A8, but they are different values. When accessing the RAM 17, the microprocessor 24 instructs the bus abiter 15 to perform DMA processing.
The write control circuit 13 and DMA read control circuit 14 are caused to output address data and manage the bus of the RAM 17. Address data output from the DMA write control circuit 13 is set in the register 16. Further, the microprocessor 24 can also access the RAM 17 without going through the DMA write control circuit 13 and the DMA write control circuit 14. Note that 33T in the data processing section 25 indicates a 3-state buffer 38T, and the impedance state of this 3-state buffer 38T is changed under the control of the microprocessor 24. The raw data area shown in FIG. 4 is used during initial operation, and the reference signals OV and vR are sent out 16 times from one signal input section.
This is an area for storing EF data for each signal input section.

Next, the operation of the analog data processing device configured as described above will be explained.

(i) During initial operation, the microprocessor 24 gives an instruction to the signal input section control circuit 10 to cause it to take in the data of the reference signal from the signal input section 61. Then, the signal input section control circuit 10 starts the timer 11 and sends data specifying the signal input section 61 via the control bus 9. Then, the timer 11 sends out an operation start signal at a period T as shown in FIG. Then, the signal input section 61 receives this, and the control circuit 5 opens and opens the switch at the timing shown in FIG. 2, OV, vREF, A1, A2, .
, A8 data is scanned. These data are digitized and sent to RAM1 via data bus 7.
Sent to 7. The microprocessor 24 has OV, VR
EF (so that only D data is stored in RAM 17,
A memory enable signal etc. is sent to RAM1 at a predetermined timing.
Give to 7. Note that the address of the RAM 17 is the address of the control circuit 5.
The output is decoded by the address decoder 12. This operation is performed 16 times here. next,
The microprocessor 24 causes the signal input sections 62 to 6° to perform similar operations. On the other hand, the microprocessor 24 has RAM 17 L (i 75
1 to OV, VREF (When D data is applied and stored 16 times, the signal input section 61 is inputted in the interval for storing data from the next signal input section 6□ to 6n (for example, when transferring A1 to A8). Offset correction data for operational amplifier 2○
and create gain correction data Gm.

That is, the data of 16 times of OV by the signal input section 61 is read from the RAM 17, the calculation of 10Vk/16...-(1) is performed on Ql, and the offset correction data 0Ill of the calculation result is stored in the RAM 18. (the area of ADCOl in FIG. 2). Similarly, 16 times of VREF data is read from the RAM 17, the following calculations are performed, and the calculation results are stored in the corresponding area of the gain correction data GIIleRAM1B (ADCGI area in FIG. 2). In the above, VRE
Fi is determined as follows. For example, VREF =
10II, V, and the gain of operational amplifier 2 is (x 1
00), and the value VREFT when the output of the operational amplifier 2 is digitized by the 16-bit A/D converter 4 (sine 1 bit + 15 bits) corresponds to 32,000. After this. When the gain of the operational amplifier 4 changes with temperature or with time, the output of the A/D converter 4 becomes VREFi. The gain correction data GIIl at that time is obtained by the above equation (2). Thereafter, each time data is collected in the RAM 17, offset correction data and gain correction data for the operational amplifiers 2 of the signal input sections 162 to 16n are created in the same manner and stored in the corresponding areas in the RAM 18, as shown in FIG. Create a memory data table like this.

This completes the initial operation.

(ii) During continuous operation.

According to instructions from the microcomputer 24, the signal input section 6
At the timing from 1 to 2, OV, ■REF,
The operations until the data of A1, Δ2, . . . A8 are sent out are the same as in the case (i) above.

However, the control circuit 5 uses the corresponding offset correction data ADCO shown in FIG. 2 as the address data of the RAM 1B.
Indicate the area of I and the area of gain correction data ADCG1. As a result, the offset correction data ADCO1 and the gain correction data ADCG1 are output from the RAM 17.
are read out and set in registers 19 and 20, respectively. On the other hand, the digital data of A1 to 88 is sent to the adder 2.
1, and is added to the offset correction data ADCO1 and sent to the multiplier 22. The multiplier 22 multiplies the offset-corrected digital data A1 to A88 by the gain correction data ADCGI to obtain corrected data. This corrected data is
Under the control of the microprocessor 24, the data is stored in the area shown in FIG. 4 of the RAM 17 (FIG. 2). below,
Similar operations are performed for the signal input units 62 to 6o,
The digital data A1 to A8 sent from the signal input sections 6□ to 6o are similarly processed and stored in the RAM 17 as shown in FIG.

When all the corrected data is collected, the microprocessor 24
starts the DMA read control circuit 14 and sends the corrected data to the CPU al via the interface 71.

On the other hand, during continuous operation, the MITE 10 processor 24 outputs signals from each signal input section 61 to 6 at a predetermined period (for example, every minute).
o's offset correction data ADCOI and gain correction data ADCG1 are updated. At the time of this update, an instruction is given to the signal input section control circuit 10, and the signal input sections 61 to 6
The control unit 5 of o stores the data of OV and VREF.
The address of AM18 is output (that is, the same operation as in the initial operation is performed). by this,
Ov,■81. The data (-times) are stored at a predetermined address in the raw data area of the RAM 1B (at the beginning of the area separated for each signal input section). For example, the signal input section 6
The Ov data obtained when updating from 1 is Oh, VRE
If the data of F is Gh, the microprocessor 24 generates new offset correction data OI! In order to obtain IN and gain correction data GlIIN, old offset correction data OI, l and old gain correction data Gm are read from the corresponding area of the RAM 18. 0IIIN=(157
16) OIIl+(1/16)Oh...(3) is calculated, GmN-(15/16) 07 + (1/16)X
[Value corresponding to A/D converter 4/(Gh-OmN>1・
...(4) Perform the calculation and obtain the OI, IN, and GIT
Each IN is stored in the corresponding area of the RAM 18.

In this way, according to the present embodiment, the signal input sections 61 to 6
Corrected data is obtained only with the analog data processing section consisting of the data processing section 25 and the data processing section 25, so
81 load can be reduced. In addition, in the correction circuit 23 for obtaining corrected data, an adder 21 and a multiplier 2
Since 2 performs calculations using hardware, it is faster than calculations using software.

Furthermore, since the microprocessor 24 updates the correction data at a predetermined period, even if the offset level and gain of the operational amplifiers 2 of each signal input section 61 to 6o fluctuate due to temperature changes or changes over time, high accuracy can be maintained. It is possible to obtain corrected data.

In this embodiment, the OV and VREF data were obtained 16 times in the initial operation to create the correction data, but the data may be obtained 16 times or less or more than 16 times.

[Effects of the Invention] As explained above, according to the present invention, since the obtained data is corrected by this device, the correction is performed by hardware without imposing a load on the CPU of the host. Since the correction value data can be updated, analog data can be processed at high speed and with high accuracy.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is a memory map of RAM 1B in which correction data is stored, FIG. 4 is a memory map of RAM 17 in which raw data and correction data are stored, and FIG. 5 is a timing chart for explaining the operation of the embodiment shown in the figure. 1 is a block diagram of a system including conventional analog data equipment. 2... Operational amplifiers 61, 62,..., 6n... Signal input section 17...
RAM 18... RAM (correction data storage section) 21... Adder 22... Multiplier 23... Correction circuit
24...Microprocessor 25...Data processing section

Claims (2)

[Claims] (1) A signal input section that includes an amplifier that amplifies the input signal, takes in the reference signal and the signal to be measured, amplifies them, digitizes them, and outputs them; and an offset based on the digital data of the reference signal given from this signal input section. a correction data creation section that creates correction data and gain correction data; a correction data storage section that stores data created by the correction data creation section; and a measurement target signal given from the signal input section. an adder that extracts and adds offset correction data corresponding to the digital data from the correction data storage section to the digital data of the signal to be measured, and adds gain correction data that corresponds to the digital data of the signal to be measured to the output of the adder. An analog data processing device comprising a multiplier that extracts data from the correction data storage section and multiplies the data. (2) Claim (1) characterized in that the correction data creation unit updates the correction data at a predetermined period.
The analog data processing device described in Section 1.