JPS62219849A - Code density detector - Google Patents

Abstract

PURPOSE:To detect a highly speedy and correct code pattern compared with the pattern used for an analog measurement by measuring digitally the total number, during the number of times equivalent to the number of steps of a delaying means, namely, measuring the total number of the number of '0' or '1' during the period divided by '1' or '0'. CONSTITUTION:A counter 11 executes the counting while a lock synchronized to the code transmitting speed of serial data is impressed, when a signal '1' arrives, the counting value of the counter 11 is stored into a buffer register 14 by the low level electric potential to show the arrival, the counter 11 is reset by the pulse at the high level of an inverter 12 and the pulse is supplied as the shifting signal of a first-in first-out memory 15. The numeric value from the buffer register 14 is added with the numeric value from an adder 16 and a subtracter 17, and stored into a register 18 by the pulse delayed with a delaying circuit 13 only for the pulse calculating necessary time of an arrived '1'. Thus, since the aggregate amount of the counting value of the counter 11 during the updated (n) number of times of the period is always stored in the register 18, a using device 19 can find the density of '0' in the serial data by the numeric value.

Description

[Detailed Description of the Invention] [Summary] Counting means for counting the number of "0" or "1" within a period separated by 1" or "0" in serial data, and a count value of this counting means , a calculation unit, and a storage unit for storing the output of the calculation unit; By subtracting the count value delayed by the means, “θ” in the serial data is
” or the density of “1” is detected.

[Industrial application field]

If there are many consecutive 40'' or 1's in the serial data, an abnormality such as the inability to extract the clock may occur in the signal processing circuit. It is necessary to detect the density of θ'' or “l”.

[Prior art and problems to be solved by the invention] Conventional technology for detecting the density of "0" or "1" integrates a serial signal and detects the density based on fluctuations in the output analog voltage. However, this method has the serious drawback that not only is the operation unstable, but it is also impossible to specifically determine the period during which the density was detected.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides a counting means 1 for counting the number of binary codes existing in a period separated by one code, as shown in the principle diagram of FIG. The output value of the delay means 2 is subtracted from the sum of the output value of the storage means 4 and the output value of the counting means 1. This is stored in the storage means 4 of the lever, so that the total number of the other codes within the plurality of periods is obtained as the count value of the storage means 4.

[For production]

The number of O'' or ``1'' within the period delimited by 1'' or 0'' in the serial data is counted by the counting means 1, and each time an ``l'' or ``O'' arrives, the arithmetic unit 3 and The count value of this counting means is sent to the n-stage delay means 2.

In the initial state, since both the storage means 4 and the delay means 2 are reset, an arithmetic operation unit that subtracts the output value of the delay means 2 from the sum of the output value of the counting means 1 and the output value of the storage means 4 The output value of 3 becomes the output value of the counting means 1, and this value is the number of "0" or "1" in the first period separated by "1" or "0", and this value is stored in the storage means 4. Stored in

Assuming that the number of stages of the delay means 2 is two, the next time the second count value is sent out from the counting means 1, the delay means 2 does not produce an output yet, so the arithmetic unit 3 stores the memory means 4. The number of "0" or "1" in the above first period stored by the counting means 1 is added to the number of "0" or "1" in the second period from counting means 1, and therefore this adder The output value is the sum of the count value of the first period and the count value of the second period, and the storage means 4 stores the count value of the first period and the second period.
The numerical value of the sum of the numbers of "0" or "l" during the period is stored.

When the count value for the third period is sent out from the counting means 1, the count value for the first period is output from the delay means 2, and the arithmetic unit 3 calculates the count value for the first period and the second period from the storage means 4. The output value of the delay means 2, which is the count value of the first period, is subtracted from the value obtained by adding the count value of the third period from the counting means 1 to the sum of the count values of the period.

As a result, the value outputted from the arithmetic unit 3 and stored in the storage means 4 becomes the sum of the count values in the second and third periods.

In this way, the numerical value stored in the storage means 4 is "1" or 0, which corresponds to the number of stages n of the delay means 2.
”, the density of 0 or 1 can be found by dividing this number by the number of stages n of the storage means, but even if it is as is, ” or “1” density can be used as an index.

〔Example〕

FIG. 2 shows an embodiment of the present invention, in which a counter 11,
The inverter 12 and the buffer register 14 are connected to the counting means 1 in FIG. 1, the first-in-first-out memory 15 is connected to the delay means 2 in FIG. The registers 18 respectively correspond to the storage means 4 in FIG.
This example is applied to pattern detection when serial data as shown in (a) is transmitted as a signal as shown in (b) of the figure.

A clock synchronized with the code transmission speed of the serial data is applied to the counting terminal of the counter 11 for counting. When a signal "1" arrives, the low level potential indicating this "1" causes the counter 11 to The count value is stored in the buffer register 14 and the inverter 12 applies a high level pulse to the reset terminal of the counter 11 to reset this counter and also provides this pulse as a shift signal for the first-in-first-out memory 15. .

In this way, the counter 11 continues counting clocks during the period when the signal shown in Figure 3 is at a high level indicating "0", and is reset by the arrival of a pulse indicating "1". The counter will count the number of "O"s within the period delimited by the "1" pulses, and this count will be stored in the buffer register 14.

This numerical value from the Ba Nofa register 14 is added to the numerical value from the subtracter 17 by an adder 16, and the arrived "1"
The pulse indicating " is delayed by the delay circuit 13 by the time required for calculation, and is stored in the register 18. However, when the count value of the counter 11 for the first period is sent from the buffer register 14, the register 18 has been reset and there is no output from the first-in-first-out memory 15 yet, so the count value of the counter 11 in the first period is stored in the register 18 as is.

The above operation continues until there is an output from the first-in-first-out memory 15, that is, until the count value of the nth period corresponding to the number of stages n of the first-in-first-out memory 15 is output from the buffer register 14. The register 18 stores the cumulative value of the bone count counted by the counter 11 for n periods.

When the count value of the counter 11 for the n+1 period is output from the buffer register 14, the first-in-first-out memory 15 outputs the count value for the first period, and the subtracter 17 outputs the count value stored in the register 18. This first counted value is subtracted from the numerical value, sent to the adder 16, added to this n+1th counted value, and sent to the register 18.
Store in.

In this way, as explained earlier, this register 1
Since the cumulative total of the count value of the counter 11 for the latest n periods is always stored in register 18,
According to the value of “θ” in the serial data, the utilization device 19
You can know the density of

The above explanation is about serial data in which each bit of the serial data is assigned to a predetermined time slot and the data indicating "l" is at a low level, but the format of the serial data is different for each bit. indicated by positive and negative pulses, or “l”, ’O”
It is clear that the code pattern can be detected by the same processing as described above, regardless of the polarity corresponding to the polarity.

〔Effect of the invention〕

According to the present invention, it is possible to digitally measure the total number of "O"s or "1s" in a period divided by "l" or "O", the number of times corresponding to the number of stages of delay means. , it is possible to detect code patterns faster and more accurately than in the analog measuring method described above.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is an embodiment of the present invention, and FIG. 3 is a diagram explaining input serial data in this embodiment. 1 is a counting means, 2 is an n-stage delay means, 3 is an arithmetic unit, and 4 is a storage means.

Claims (1)

[Claims] Counting means (1
), an n-stage delay means (2) to which the count value of the counting means is supplied, an arithmetic unit (3) and a storage means (4), and the arithmetic unit is configured to calculate the output value of the counting means and the output value of the counting means. By subtracting the delayed output value from the delay means from the total value with the output value of the storage means, the total value of "0" or "1" in the plurality of divided periods is obtained and stored in the storage means. A code density detection device characterized in that the code density is stored in a means.