JPS62217635A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent etching of even a field oxide film and to prevent short circuits between a wire interconnecting layer and a substrate, by providing a contact hole so that it is wider than a gate electrode, and making a polycrystalline silicon pattern to be functioned as a stopper at this time. CONSTITUTION:A polycrystalline silicon pattern 11 is formed on a field oxide film 2. A thermal oxide film 12 is formed on the surface of the pattern. The resistance of the pattern 11 is very high. The width of the pattern 11 is wider than a gate electrode 6. A contact hole 13 is provided in a CVD-SiO2 film 7 at a position of the pattern 11. The hole 13 is formed so that it is so wide as to extend to the outside of the electrode 6 and it is located within the inside of the pattern 11. Then, etching in forming the hole 13 is stopped by the pattern 11. Thus the etching of even a field oxide film 2 is prevented, and short circuits between a wire interconnecting layer and a substrate 1 are prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to a connection structure between wiring layers in a multilayer wiring.

(Prior Art) Connections between wiring layers in a semiconductor device using multilayer wiring are generally made by forming contact holes in an insulating film between the eyebrows. For example, in a MOSO8 type semiconductor device, when connecting a metal wiring layer II formed as a second layer wiring to a gate electrode made of a polycrystalline silicon layer formed as a first layer wiring, as shown in FIG. A contact structure as shown in >(B) has been conventionally employed. Note that FIG. 2(A) is a cross-sectional view along the channel region of the MOS transistor portion, and FIG. 1(B) is a plan view.

In these figures, 1 is a P-type silicon substrate. The surface of the silicon substrate 1 is selectively field oxidized 8!
$2 is formed, and this field oxide film makes the MOS
The element region of the transistor is surrounded. In the device region, an N1 type source region 3 and drain region 4 are formed which are spaced apart on both sides of the channel region. A gate electrode 6 made of a polycrystalline silicon layer is formed on the channel region via a gate oxide t15, and both ends of the gate electrode 6 extend above the field oxide 112. This gate electrode is CVD-8IO2N
It is covered with an I (interlayer insulating film) 7, and aluminum wiring is formed on the interlayer insulating film. In order to connect this aluminum wiring layer to the gate electrode 6, CV
Contact hole 8 is opened in D-8i 021117. The contact hole is formed on one end of the gate electrode 6. With the miniaturization of devices, reactive ion etching (RIE) has come to be used to form contact holes. In that case, contact hole 8
In consideration of the mask misalignment in PEP that forms the
As shown in Figure (B), the contact portion of the gate electrode 6 is formed to be enlarged by a corresponding margin A.

(Problems to be Solved by the Invention) As described above, in conventional semiconductor devices, a margin A is provided in the contact portion of the gate electrode for mask alignment misalignment, which hinders miniaturization. be.

On the other hand, if this margin A is not provided, when the position of the contact hole 8 protrudes outside the gate electrode 6 due to misalignment of the mask, the field oxide film 2 will also be etched during RIE processing, so in the worst case is aluminum wiring 9
This results in a problem that the wafer is short-circuited with the silicon substrate 1.

The present invention has been made in view of the above circumstances, and it is possible to miniaturize and highly integrate a semiconductor device having multilayer wiring on a semiconductor substrate without causing a short circuit between the wiring and the semiconductor substrate.1. Another purpose is to reduce contact resistance between wirings.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor device according to the present invention includes a first interconnection laM formed on a semiconductor substrate on which an element is formed via an insulating film, and a A second wiring layer formed on the wiring via an insulating film, and a contact hole formed at a predetermined position in the insulating film interposed between the first and second wiring layers to connect them. The width of the contact hole is made wider than the width of the first wiring layer, and at least at the position of the contact hole, an etching protective film is provided under the first wiring layer 1sWI as an etching protection film for the insulating film thereunder. It is characterized by having a functional high-resistance film interposed in a wider area than the contact hole.

As the high-resistance film in the present invention, any film may be used as long as it has a sufficient etching selectivity with respect to the above-mentioned absolute R film and has a high specific resistance. For example, as the insulating film, Si
If an O2 film is used, a polycrystalline silicon layer or a silicon nitride film can be used.

(Function) In the semiconductor device of the present invention, the contact hole is formed wider than the first wiring layer, but since the high-resistance film is present in the portion protruding from the first wiring layer width, Etching during contact hole formation is prevented by this high resistance coating.

Therefore, it is possible to prevent a contact hole from being formed through the interlayer insulating film therebelow. Therefore, there is no need to enlarge the contact part of the first layer wiring as in the past.
Miniaturization and high integration can be achieved. Moreover, since there is no need to consider electrical short circuits due to the high resistance film, this can be shared by a plurality of contact holes.

In addition, since the contact hole is formed wider than the width of the first wiring layer, the second wiring layer also comes into contact with the sidewall of the first wiring layer.

Therefore, the contact area between the two is wider than the conventional one by the contact area on the side wall, and the contact resistance is reduced.

(Embodiment) FIG. 1(A) is a pattern plan view showing an embodiment of the present invention applied to a MOS type semiconductor device, and FIG. 1(B) is a sectional view along the channel region thereof. In these figures, the same parts as in FIG. 3 are designated with the same reference numerals. That is, 1 is a P-type silicon substrate, 2 is a field oxide film, 3 is an N+ type source region, 4 is an N+ type drain region, 5 is a gate oxide film, and 6 is polycrystalline silicon whose resistance has been lowered by doping with impurities. gate electrode consisting of layers,
7 is CVD-8i 0211! It is. Since these structures are the same as those of the conventional example shown in FIG. 3, their explanations will be omitted.

In addition to the above configuration, in this embodiment, the field oxide film 2
An undoped polycrystalline silicon pattern 11 is formed thereon, and a thermal oxide film 12 is formed on the surface thereof. Since the polycrystalline silicon pattern 11 is not doped with impurities, its resistance is extremely high. One end portion of the gate electrode 6 is laminated to extend over the polycrystalline silicon pattern 11. As shown, the width of the polycrystalline silicon pattern 11 is wider than the gate ff electrode 6, and the end of the gate electrode 6 is completely contained within the region.

Further, in this embodiment, the polycrystalline silicon pattern 11
Contact hole 1 in CVD-8iO2 hole 7 at the position of
3 is drilled. As shown, the contact hole is connected to the gate 'R1! wide so as to protrude outside of ii,
Moreover, the hole is opened so as to fit inside the polycrystalline silicon pattern 11. The thermal oxidation 1[112 on the surface of the polycrystalline silicon pattern 11 is to prevent impurities in the gate electrode 6 from diffusing into the polycrystalline silicon pattern and lowering the resistance.

According to the above embodiment, the contact hole 13 is opened wider than the gate electrode 6, but at that time, the polycrystalline silicon tavern 11 functions as a stopper to prevent etching down to the field oxide film 2. It can be prevented. Therefore, a short circuit between the aluminum wiring layer and the silicon substrate as described in FIG. 4 does not occur. As a result, there is no need to enlarge the gate electrode by the margin A in consideration of mask misalignment in the conventional example shown in FIG. 3, and the device can be miniaturized and highly integrated. Moreover, as is clear from FIG. 1<8), the aluminum wiring formed on the CVD-5iO2 film 7 contacts not only the surface but also the side surfaces of the gate electrode 6 through the contact hole. Therefore, the contact area is increased by the contact area on the side surface compared to the conventional one, and the contact resistance can be lowered to increase the speed.

FIG. 2 is a pattern plan view showing another embodiment of the present invention.
According to this embodiment, the effects regarding miniaturization and high integration of the device can be more clearly understood.

In Figure 2, two MOSs are paired as shown.
Transistors are arranged facing each other at one end of the gate electrode. The ends of each gate electrode 6.degree. 6' extend over an undoped polycrystalline silicon pattern 11' formed on the field oxide film, and are stacked so as to face each other. The surface of the polycrystalline silicon pattern 11' is covered with a thermal oxide film as in the embodiment shown in FIG. Then, on this polycrystalline silicon pattern 11, a gate! ff
contact holes 13 for each end of fi6.6'
．． 13' are opened and connected to the second layer aluminum wiring through these contact holes. In this way, even if the ends of the gates 114i6゜6' are stacked on the common polycrystalline silicon pattern 11', since the polycrystalline silicon pattern has a high resistance, the gate 7Il pole 6,
6'B short circuit does not occur.

In the embodiment of the second cause, the two contact holes 13 and 13' are opened at the same time in one PEP.
The distance between the two can be shortened to the limit possible with PEP. Similarly to this embodiment, it is also possible to share one polycrystalline silicon pattern for three or more contact holes.

Note that the polycrystalline silicon pattern 11 in the above embodiment
．． A silicon nitride film pattern may be used instead of 11', and in this case, a thermal oxide film on the surface is unnecessary.

Further, the present invention can be applied not only to the contact with the gate electrode described above but also to contact structures between various multilayer wirings.

[Effects of the Invention] As detailed above, according to the present invention, in a semiconductor device having multilayer wiring on a semiconductor substrate, miniaturization and high integration of the device are possible without causing short circuits between the wiring and the semiconductor substrate. In addition, remarkable effects such as being able to reduce the contact resistance between wirings can be obtained.

[Brief explanation of drawings]

The first factor and FIG. 2 each represent an embodiment of the present invention.
FIG. 3 is an explanatory diagram of an O3 type semiconductor device, and FIG. 3 is an explanatory diagram of a conventional MOS type semiconductor device, and FIG. 4 is a sectional view showing the problems thereof. DESCRIPTION OF SYMBOLS 1...P-type silicon substrate, 2...Field oxide film, 3.3'...N'' type source region, 4,4'...N
+ type drain region 5...gate oxide film, 6.6'
...Gate electrode, 7...CVD-8i 02 III
, 11°11'... polycrystalline silicon pattern, 12.
...Thermal oxide film, 13... Contact hole applicant's representative Patent attorney Takehiko Suzue Figure 1 (A) Figure 1 (B) Figure 2 Figure 3 (A) Figure 3 (B) Figure 4 figure

Claims (3)

[Claims] (1) a first wiring layer formed on a semiconductor substrate on which an element is formed via an insulating film; a second wiring layer formed on the first wiring layer via an insulating film; In order to connect these first and second wiring layers, a contact hole is formed at a predetermined position in an insulating film interposed between them, and the width of the contact hole is set to be smaller than the width of the first wiring layer. In addition, at least at the contact hole position, a high-resistance film that functions as an etching protection film for the underlying insulating film is interposed under the first wiring layer over a wider area than the contact hole. semiconductor device. (2) Claims characterized in that the first wiring layer is a gate electrode of a MOS type semiconductor device extending on a field oxide film, and the second wiring layer is a metal wiring layer. The semiconductor device according to item (1). (3) The semiconductor device according to claim (2), wherein the high-resistance film is an undoped polycrystalline silicon film whose surface is covered with a thermal oxide film.