JPS6221663U - - Google Patents
Info
- Publication number
- JPS6221663U JPS6221663U JP11316785U JP11316785U JPS6221663U JP S6221663 U JPS6221663 U JP S6221663U JP 11316785 U JP11316785 U JP 11316785U JP 11316785 U JP11316785 U JP 11316785U JP S6221663 U JPS6221663 U JP S6221663U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- horizontal synchronization
- synchronization signal
- pll
- detected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Synchronizing For Television (AREA)
Description
第１図は本考案のＰＬＬ用水平同期信号弁別回
路の概略ブロツク図、第２図は同水平同期信号弁
別回路のタイミングチヤート、第３図は位相同期
ループの概略ブロツク図である。
１……第１ワンシヨツトマルチバイブレータ、
２……Ｄ―フリツプフロツプ、３……第２ワンシ
ヨツトマルチバイブレータ、４……第３ワンシヨ
ツトマルチバイブレータ。
FIG. 1 is a schematic block diagram of a horizontal synchronizing signal discriminator circuit for PLL according to the present invention, FIG. 2 is a timing chart of the horizontal synchronizing signal discriminating circuit, and FIG. 3 is a schematic block diagram of a phase locked loop. 1...First one-shot multivibrator,
2...D-flip-flop, 3...Second one-shot multivibrator, 4...Third one-shot multivibrator.
Claims (1)
る回路であつて、 入力された水平同期信号に含まれている各パル
スに同期して、本来の水平同期パルスのパルス幅
より短いパルス幅を有する基準パルスが発生され
、この基準パルスと前記各パルスとのパルス幅を
比較して本来の水平同期パルスが検出され、この
検出された水平同期パルスに同期して、本来のパ
ルス幅と周期とからなる水平同期信号が出力され
るようになされたことを特徴とするＰＬＬ用水平
同期信号弁別回路。[Claims for Utility Model Registration] A circuit provided before the digital phase comparator of a PLL, which synchronizes with each pulse included in the input horizontal synchronization signal and adjusts the pulse width of the original horizontal synchronization pulse. A reference pulse having a shorter pulse width is generated, the original horizontal sync pulse is detected by comparing the pulse widths of this reference pulse and each of the above-mentioned pulses, and the original horizontal sync pulse is synchronized with the detected horizontal sync pulse. 1. A horizontal synchronization signal discrimination circuit for a PLL, characterized in that a horizontal synchronization signal consisting of a pulse width and a period is output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11316785U JPS6221663U (en) | 1985-07-24 | 1985-07-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11316785U JPS6221663U (en) | 1985-07-24 | 1985-07-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6221663U true JPS6221663U (en) | 1987-02-09 |
Family
ID=30994709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11316785U Pending JPS6221663U (en) | 1985-07-24 | 1985-07-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6221663U (en) |
-
1985
- 1985-07-24 JP JP11316785U patent/JPS6221663U/ja active Pending
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