JPS62216524A - Clock generator - Google Patents

Abstract

PURPOSE:To keep output impedance lower at H level output even when the leakage of electric charge exists in a gate by connecting a pumping circuit to the gate of an output MOS transistor (TR). CONSTITUTION:In the pumping circuit 18, a drain of a MOS TR 19 is connected to a power supply and a gate is connected in common to a source of a MOS TR 21 and also to a node N1, a gate of a MOS TR 20 is connected to the power supply, the drain and source of the MOS TR 21 are connected in common and one terminal of a capacitor 16 is connected to a common connecting node N2. When the potential of the node N1 reaches a value being the addition of the power potential and a threshold voltage due to the leakage of electric charge or below, the MOS TR 21 is turned on to keep the potential at an output termi nal C to the power supply potential. Thus, even when the leakage of electric charge exists in the node N1, the output impedance at H level output is kept low.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a clock generator constructed using MOS transistors.

Conventional technology Dynamic random access memory (hereinafter referred to as DR)
(referred to as AM), it may be necessary to maintain the internal state for a long period of time. To achieve this purpose, it is necessary to maintain the voltage value of the internal signal at a stable value, and a pumping circuit is used. FIG. 3 shows an example of a conventional circuit in which a pumping circuit is added to an internal signal generation circuit built into a DRAM, and is composed of N-channel enhancement type MOS transistors 1 to 14, capacitors 15 and 16, and a ring oscillator 17. There is. The circuit section surrounded by the broken line frame 18 is a pumping circuit, B is a terminal to which clock signal φB is applied, B is a terminal to which clock signal φB is applied, C is an output terminal, and N1 is a node. be.

In the circuit configured as described above, by applying the clock signals φM and φB shown in FIG. 4 to the terminals A and B, respectively, the signal φG shown in FIG. 4 is obtained at the output terminal C. Therefore, the logic level of the output signal φG is
4 In order to keep the clock signal φM at the ``1'' level (K), it is necessary to keep the clock signal φB at the low ``L'' level. Also, the logic level of the output signal φG must be kept at the ``L'' level. In order to maintain the IT level, it is necessary to maintain the clock signal φ at the "L" level and the clock signal φB at the "H" level.

By the way, when the output terminal C is "H" and the output signal of Bell is output, the MOS transistor 1.4 is in the on state, so the charge on the gate of the MOS transistor γ is M.
(OS) transistor 4 is pulled out, and the MOS transistor 7 is turned off. Also, the clock signal φ
Since B is at the "L" level, the MOS transistor 8 is also turned off.

Therefore, when the 'H' level is output, the node N1 is in a floating state. At this time, the potential of the node N1 becomes a value higher than the power supply potential by more than the threshold voltage due to the bootstrap effect of the capacitor 15, The potential is kept at the power supply potential.However, if the charge at node N1 leaks for some reason and the potential at node N1 becomes lower than the sum of the power supply potential and the threshold voltage, the potential at output terminal C becomes lower than the power supply potential. turn into.

In order to compensate for this drop in output potential, a pumping circuit 18 consisting of MOS transistors 13, 14 and a capacitor 16 is used. That is, the output signal of the ring oscillator 17 and the capacitor 1θ make the gate of the MOS transistor 13 higher in potential than the power supply potential by more than the threshold voltage, and the potential of the output terminal C is restored to the power supply potential.

Problems to be Solved by the Invention In the conventional circuit, if the impedance of the MOS transistor 13 is lowered, the potential of the output terminal C becomes higher when the "L" level is output.
It is necessary to keep the size sufficiently small. Therefore, when the "H" level is output and the potential of the node N1 is lowered due to charge leakage, it becomes impossible to maintain the output impedance low. At this time, if the potential of the output terminal C suddenly drops due to coupling with other signals, it will take a long time to restore this potential to the power supply potential. For this reason, the next stage and subsequent stages may malfunction during the potential recovery period.

The present invention is an N-channel enhancement type MO in which the gate potential reaches a potential higher than the power supply potential by more than the threshold voltage due to the bootstrap effect when the "H" level is output.
8) A pumping circuit is connected to the gate of the transistor to provide a generator that can maintain the output impedance at a low value for a long time even if there is charge leakage at the gate.

Means for Solving the Problems In the clock generator of the present invention, the logic level of the output changes when the logic levels of the first and second clock signals are high level and low level or low level and high level, and A first capacitor of an enhancement type is connected between the first capacitor connection node and the power supply terminal of the clock generation circuit in which the potential at high level is kept at the power supply potential due to the bootstrap effect of the first capacitor. Drain source circuits of the second and third MOS transistors are connected in cascade, and the gate of the first MOS transistor is commonly connected to the source of a third MOS transistor whose source is connected to the first capacitor connection node. and the second MO
S) The gate of the transistor is connected to the power supply terminal, and the drain and gate of the third MOS) transistor are commonly connected, and at the same common connection point, there is a second capacitor whose one end is connected to the output terminal of the ring oscillator. It has a configuration in which the ends are connected.

Operation In the clock generator of the present invention, even if there is charge leakage at the gate of the output MOS transistor, “HIT
The output impedance during level output can be kept low for a long time, and even if the potential of the output signal line suddenly drops due to coupling with other signal lines, it can be restored to the original potential in a short time. I can do it.

Embodiment FIG. 1 is a diagram showing an embodiment of the clock generator of the present invention, which is different from the conventional clock generator shown in FIG. 3 in the configuration of the pumping circuit 18. Note that circuit elements that are the same as conventional circuit elements are given the same numbers and symbols.

In the present invention, the bombing circuit 18 is an N-channel enhancement type MO8 in which drain source circuits are connected in cascade.
) transistors 19, 20 and 21, and a capacitor 16; furthermore, the drain of the MOS transistor 19 is connected to the power source, the gate is commonly connected to the source of the MOS transistor 21 and connected to the node N1, and the gate of the MOS transistor 2o is connected to the power source. In addition, the drain and source of the MOS transistor 21 are connected in common, and one end of the capacitor 16 is connected to this common connection node N2.

Even in the clock generator of the present invention configured as described above,
When the output level of output terminal C is “H” level, node N1
becomes floating. Therefore, the potential of the node N1 is kept at a voltage higher than the power supply potential by the threshold voltage or more due to the bootstrap effect of the capacitor 16.

By the way, the bombing circuit 18 performs the following circuit operation when outputting the "H" level. That is, when the output of the ring oscillator 17 is at L level, the MOS transistor 19 whose gate is connected to the node N1 and the MOS transistor 20 whose gate is connected to the power supply are turned on, while the MOS transistor 21 is turned off. state.

Therefore, capacitor 16 is MOS) transistor 1
It is charged through 9 and 20. Next, when the output of the ring oscillator 17 becomes "H" level, the potential of the node N2 becomes a value that is more than twice the threshold voltage than the power supply potential.
MOS) transistor 2° is turned off. Node N1
When the potential of the node N1 becomes lower than the value obtained by adding the threshold voltage to the power supply potential due to charge leakage, the MOS transistor 21 turns on, restores the potential of the node N1, and outputs the output terminal C.
can maintain the potential at the power supply potential. Therefore, even if there is charge leakage at node N1, the output impedance during H" level output can be kept low. Therefore, the potential of output terminal C is affected by coupling with other signal lines, and the output impedance can be kept low. Even if the potential drops, it can be restored to the original potential in a short time, and malfunctions of circuit sections in subsequent stages can be prevented.

FIG. 2 is a diagram showing another embodiment of the clock generator of the present invention, in which the output MOS transistor 11 is also used as a MOS transistor constituting a bombing circuit 18. In this configuration, MOS transistor 1
1 functions as a transistor corresponding to the MOS transistor 19 of the circuit shown in FIG. The circuit operation of the pumping circuit configured in this way is the same as that of the pumping circuit shown in Fig. 1, and even if a circuit state in which the potential of the output terminal C drops is established, the potential can be restored in a short time. can be done.

Effects of the Invention In the clock generator of the present invention, a pumping circuit is connected to the gate of the output MO8) transistor, which has a potential higher than the power supply potential by the threshold voltage due to the bootstrap effect when outputting the "H" level. Therefore, even if there is charge leakage at the gate of the output MOS transistor, the output impedance at the time of "H" level output can be kept low. Therefore, although it is a dynamic circuit, static operation is also possible. Furthermore, even if the output potential drops suddenly due to coupling with other signal lines, this potential can be recovered in a short time to prevent malfunctions in the next stage and subsequent stages. Therefore, the 0

[Brief explanation of drawings]

1 and 2 are circuit diagrams showing the configuration of a clock generator in an embodiment of the present invention, FIG. 3 is a circuit diagram showing the configuration of a conventional clock generator, and FIG. 4 is a waveform of input/output pulses. This is a timing chart showing the timing. Person, B...Clock signal application terminal, C...
...Output terminal, 1-14.19-21...N-channel enhancement type MOS transistor, 15.
16... Capacitor, 17... Ring oscillator, 18... Bumping circuit, N1.
N2...Node. Name of agent: Patent attorney Toshio Nakao and one other person C.
--totoachechi N+, It-・-Sho A. IJ2 diagram

Claims (2)

[Claims] (1) The logic level of the output changes due to the logic levels of the first and second clock signals being high level and low level or low level and high level, and the bootstrap effect due to the first capacitance causes the output to change at high level. Drain-source circuits of first, second, and third enhancement-type MOS transistors are connected in cascade between the first capacitor connection node and the power supply terminal of a clock generation circuit whose potential is maintained at the power supply potential. ,moreover,
The gate of the first MOS transistor is commonly connected to the source of a third MOS transistor whose source is connected to the first capacitor connection node, the gate of the second MOS transistor is connected to a power supply terminal, and the third MOS transistor A clock generator characterized in that the drains and gates of the transistors are commonly connected, and the other end of a second capacitor, one end of which is connected to the output terminal of a ring oscillator, is connected to the common connection point. (2) The clock generator according to claim 1, wherein an output MOS transistor in the clock generation circuit also serves as the first MOS transistor.