JPS62216221A - Compound semiconductor crystal substrate and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a substrate having high performance, large area, ready wiring and high economy by forming a plurality of recesses formed of two types of surfaces on a silicon supporting crystal substrate and covering it with compound semiconductor crystal through specific steps. CONSTITUTION:A silicon supporting crystal substrate 1 has on its one surface a plurality of recessed formed of 111 and 100 surfaces, a compound semiconductor crystal layer 3 for forming a semiconductor element disposed in the recesses, and a thin film 2 made of an insulation material formed on the projections of the substrate 1 having tops divided by the adjacent recesses of 100 surface. At least part of the film 2 is covered with the crystal 3, and continued to the layer 3 for forming adjacent semiconductor elements. Thus, the surface becomes flat, a wiring pattern necessary when integrating an element on the large area substrate is disposed on the layer 3 for connecting adjacent element regions to be readily formed, and no crack occurs on the crystal layer.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a compound semiconductor crystal layer in which a compound semiconductor crystal layer is formed on a silicon supporting crystal layer, and a method for manufacturing the same. (problems to be solved) Compound semiconductors have traditionally been used in lasers and LEDs.
, optical devices such as solar cells and junction transistors,
It has been used in electronic devices such as field effect transistors, and more recently in so-called opto-electronic devices that integrate optical devices and electronic devices.The above devices use a compound semiconductor crystal as a supporting substrate, and a compound semiconductor layer is formed on the supporting substrate. Devices were fabricated by epitaxial growth. However, supporting substrates for compound semiconductor crystals are not only expensive, but also have many defects, making it difficult to obtain crystal substrates with large areas. To solve these problems, we support silicon crystal, which is inexpensive, has a large area, and has established mass production technology, in order to take advantage of the advantages of compound semiconductors and obtain large-area, highly economical compound semiconductor devices. Attempts have been made to create devices with a large area, low cost, high performance, and multifunctionality by fabricating devices on a compound semiconductor crystal layer using silicon as a substrate and forming a compound semiconductor crystal layer on top of a silicon supporting crystal layer. ing. However, when forming a compound semiconductor crystal layer on a silicon supported crystal layer by epitaxial growth, lattice defects and distortions occur in the compound semiconductor crystal layer due to the difference in thermal expansion coefficient between the silicon supported crystal layer and the compound semiconductor crystal layer. This not only makes it impossible to obtain a high-quality compound semiconductor layer suitable for producing the above-mentioned optical devices, electronic devices, and opto-electronic devices, but also
When a compound semiconductor crystal layer is formed over a large area or when a compound semiconductor crystal layer is formed thickly, there are problems such as rainbow cracks due to thermal stress, making the substrate unusable as a substrate for producing a heel device. As a method to solve these problems, it has been considered to form a compound semiconductor crystal layer by dispersing compound semiconductor crystals in the form of islands on a silicon supporting crystal layer. In this case, a pattern made of an insulating material is formed on the silicon support crystal layer as shown in FIGS. The compound semiconductor crystal layer is selectively grown and dispersed in island shapes. In addition, Fig. 5 (a), (b)
1A and 1B show a plan view and a cross-sectional view, respectively, of a case in which a notch made of an insulating material is formed on a silicon crystal layer.

FIG. 5(c) further shows a cross-sectional view after the compound semiconductor crystal layer is completely formed. In the figure, 1 is a silicon support crystal layer, 2 is an insulating material baton on which the silicon support crystal layer is formed, and 3 is a compound semiconductor crystal layer. In this case, the compound semiconductor crystal layer is dispersed and formed into islands, and the problem described above is the occurrence of cracks caused by thermal stress due to the difference in thermal expansion coefficient between the silicon support crystal layer and the compound semiconductor crystal layer. However, when integrating all the elements on a large-area substrate, another problem arises in that the formation of the necessary wiring pattern is impossible due to the step difference caused by separating the compound semiconductor crystal layer into islands. do.

Furthermore, MBE and MOCVD methods have been developed as conventional methods for growing compound semiconductor crystals on a silicon supported crystal layer, but insulating materials (such as 5i02
), and the polycrystalline compound semiconductor grows on the insulating material, making it impossible to grow a compound semiconductor crystal covering at least a portion of the insulating material.

Also, by any conventional method (100).

There were problems in that the growth rate ratio of the (111) compound semiconductor crystal could not be large enough, and the cross-sectional shape after growth became uneven as shown in FIG. 6, making wiring difficult.

However, the chloride VPE method and hydride VPE method, which are widely applied to compound semiconductor crystals, have a remarkable selectivity, but the HCl contained in the reaction gas corrodes the quartz glass used in the reaction tube, generating Hlo. . This H
There is a problem in that when 2O is transported onto a silicon substrate, it oxidizes the silicon surface and inhibits the growth of compound semiconductor crystals.

(Problem tl - Means for Solving) The present invention has been proposed to solve the above problems, and is a high-performance, large-area, easy-to-wire, and economical compound semiconductor crystal layer. The purpose is to provide a manufacturing method.

In order to achieve the above object, the present invention provides silicon (100%
) Place the compound semiconductor crystal layer with the compound semiconductor crystal layer with the supporting crystal layer on top, and place the silicon supporting crystal layer on the surface (
111) and (Zoo),
A compound semiconductor crystal layer for forming a semiconductor element is disposed in the recess, and the top part dividing adjacent recesses is (10
0) in which a thin film of an insulating material is provided on the convex portion of the silicon supporting crystal layer, at least a portion of the thin film is covered with a compound semiconductor crystal, and a compound semiconductor for forming the adjacent semiconductor elements; The gist of the invention is a compound semiconductor crystal layer characterized by being continuous with a crystal layer.

Furthermore, the present invention includes a step of forming a plurality of concave portions consisting of (111) and (100) on an St (100) substrate, and epitaxially growing a compound semiconductor crystal on the substrate so that each concave portion is at least partially continuous. The gist of the invention is a method for manufacturing a compound semiconductor crystal layer, which comprises a step of filling the compound semiconductor crystal layer with a compound semiconductor crystal layer.

The most important feature of the present invention is that a plurality of recesses are formed on the plane of the silicon support crystal layer, and the compound semiconductor crystal layers forming the semiconductor element formed in the recesses are at least partially continuous with each other. This is different from the conventional technique in which a hole made of an insulating material is formed on a silicon support crystal layer and the compound semiconductor crystal layer is arranged so as to be completely separated into islands. Embodiments of the present invention will now be described with reference to the accompanying drawings. The examples are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention. Detailed description of the invention.

FIG. 1 shows the main steps in one embodiment of the present invention. In the figure, 1 is a silicon supporting crystal layer, 2 is a batten made of 5iOz which is an insulating material, 3 is a compound semiconductor crystal layer, and 4 is a silicon support crystal layer. It's a resist slam. Silicon oxide 2 is formed to a thickness of 0.5 μm on a silicon supported crystal layer 1 of (ioo) by thermal oxidation method or snow vine method. Form a button in the shape (Figure 1a). Next, using the resist batten as a mask, 5iOzt-etching is performed using HF aqueous solution or dry etching using CT F6 gas, etc. to give the desired shape, and then silicon is used as a 5iOt2t mask. The supporting crystal layer is etched by 4 μm with a KOH aqueous solution to form a concave portion (see Figure 1). The above silicon etching solution has a selectivity in which the etching speed of Bit) is slow and the etching speed of (Zoo) is fast. Any etching liquid may be used. Further, the thickness of the oxide film is not limited to the above thickness as long as it remains after silicon etching is completed. Furthermore, the etching depth of silicon is merely an example and is not limited thereto.

Next, a compound semiconductor crystal layer 3 (c
) The method devised by the present inventor is suitable, for example. 16 is a reaction tube, and a gas inlet 11.
12 and an outlet 15 are provided, and 17 is a crystal holder, on which a silicon support crystal layer 14 is placed. This substrate 14 selectively takes the position shown by the solid line and the position shown by the broken line. 013 indicates a Ga source.

To grow a compound semiconductor crystal, a silicon support crystal layer is placed at the position shown by the broken line in FIG. The temperature distribution in the zero-order reaction tube 16 is set as shown in FIG. 2(b).
Source 13't800°C, substrate position t-350°
Keep it. Next, the inlet 11, a mixed gas of 9PH and
A mixed gas of HCt and gas is introduced through the inlet 12, and after the flow becomes steady, the substrate 14 is moved to the position shown by the solid line in the second position (second fixation) and held for 2 minutes to carry out the first step. , return the substrate to the position indicated by the broken line in Fig. 2(a), raise the substrate temperature to 600°C, move it again to the position indicated by the solid line in Fig. 2(a), hold it for 10 minutes, and then Perform the second process of returning to position. By repeating the above second step 10 times, the silicon supporting crystal layer is placed on top of the silicon supporting crystal layer as shown in FIG.
A GaP crystal grows as shown in c). The first step in the above growth method is as shown in FIG.
o) The growth rate is different between the top and (111) top, ri (1
11) Only an extremely thin film grows under the above conditions.

Therefore, when the temperature is raised to carry out the second step, the film evaporates and only the (111) silicon surface is exposed. At the temperature of 600°C in the second step, the oxidation rate of silicon is Ga
Since the growth rate is faster than that of P, in (111), an oxide film is formed at the same time as the exposed silicon moves the substrate for growth, inhibiting the growth of GaP. On the other hand, in (100), GaP is grown in the film grown in the first step to prevent oxidation of silicon.

As explained above, in the above method, since there is no unnecessary growth from (111), the concave portion of the 0 silicon supporting crystal layer, which grows without disturbing the flatness of (100), is made of Ga.
After being filled with P crystals, GaP crystals grow in the lateral direction on the 5iOz insulating pattern 2, as shown in Fig. 1 (
The structure c) is realized.

FIG. 4 shows a second embodiment.

In this embodiment, as shown in FIG. 4(a), there is no batten 2 made of the insulating material shown in FIG. 1.

In the manufacturing process of the first embodiment, Sin and the slam width are set to 0.
．． The same is true except that the thickness is about 5 μm. That is, K.O.
Selective etching of silicon with H aqueous solution is shown in Figure 4 (
In b), the etching amount A of (100) and (111)
Since the ratio of the etching amount B is A:B=25:1,
When Ak is 5 .mu.m, the side etch ilB is 0.4 to 0.5 .mu.m including the left and right sides, and the shape shown by the solid line is obtained. By carrying out the first example using the above substrate, a compound semiconductor substrate shown in FIG. 4(b) is obtained.

Generally, when a compound semiconductor crystal is grown with a uniform thickness on a silicon supported crystal layer, efclaration occurs due to the stress caused by the difference in the coefficient of thermal expansion between the two, but in the substrate according to the present invention, the compound semiconductor No cracks occurred because the stress was relaxed in the region where the crystal thickness was thin.

In the above embodiments, GaP is described, but GaAs is used.

It can be similarly realized using other compound semiconductor crystals such as InP.

(Effects of the Invention) As explained above, according to the present invention, a silicon supporting crystal layer is formed of (111) and (100) planes to form a recessed part, and the compound semiconductor crystal layer is covered with a compound semiconductor crystal. Therefore, when devices are integrated on a large p-area substrate with a flat surface, the wiring tabs required can be easily formed by placing them on the compound semiconductor crystal layer connecting adjacent device regions. Further, because of the above structure, cracks do not occur in the compound semiconductor crystal layer, and an element using a compound semiconductor crystal on a silicon substrate can be realized.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of the process of manufacturing a compound semiconductor crystal layer of the present invention, Figure 2 (a) is a conceptual diagram of the growth apparatus, Figure 3 is the temperature distribution, and Figure 3 is (100). . Time dependence of the thickness of GaP grown on the (111) surface, Figure 4 (a) is the second embodiment of the present invention, Figure 5 (a) is a diagram explaining the amount of silicon etched by a KOH aqueous solution, Figure 5 The figure is a schematic diagram showing a conventional compound semiconductor crystal layer, and FIG. 6 shows a compound semiconductor crystal layer grown by the conventional method. 1... Silicon support crystal layer 2...
・・・・・・Battle 3 made of insulating material・・・・・・・・・
- Compound semiconductor crystal layer 4... Resist button 11.12... Gas inlet 13... Cap source 14... Silicon support Conclusion board 15...
......Gas outlet 16...Reaction tube 17...Substrate holder 4°-resist/tan Fig. 3 Fig. 4

Claims (3)

[Claims] (1) A compound semiconductor crystal substrate including a compound semiconductor crystal layer on a silicon {100} supporting crystal substrate, having a plurality of recesses composed of {111} and {100} on the surface of the silicon supporting crystal substrate; A compound semiconductor crystal layer for forming a semiconductor element is disposed in the recess, and a thin film of an insulating material is provided on the convex part of the silicon supporting crystal substrate whose top part is {100} which separates the adjacent recesses, 1. A compound semiconductor crystal substrate characterized in that at least a portion of the thin film is covered with a compound semiconductor crystal and is continuous with an adjacent compound semiconductor crystal layer for forming the semiconductor element. (2) In a compound semiconductor crystal substrate comprising a compound semiconductor crystal layer on a silicon {100} supporting crystal substrate,
11} and {100}, a compound semiconductor crystal layer having a thickness exceeding the height of the asperities is provided on a silicon support crystal substrate having concavities and convexities constituted by {100}, and at least one of the compound semiconductor crystal layers on adjacent concave portions is provided. The compound semiconductor crystal substrate according to claim 1, wherein a portion of the compound semiconductor crystal substrate is continuous. (3) {111} and {100} on Si {100} substrate
and a step of epitaxially growing a compound semiconductor crystal on the substrate and filling each recess with a compound semiconductor crystal layer so that at least a portion of the recess is continuous. Method for manufacturing a crystal substrate.