JPS62214596A - Semiconductor circuit device - Google Patents

Abstract

PURPOSE:To quicken the read operation by connecting a MOSFET in parallel with a nonvolatile memory cell, conducting the FET for a prescribed time just after the write and discharging the remaining charge of a drain line of the nonvolatile memory cell. CONSTITUTION:A control signal the inverse of phi6 related to the write f a FAMOS 1 is inputted to a circuit 10. The circuit 10 uses CMOS inverters 11a-11e, gates 13a, 13b comprising CMOSFETs 12a, 12b and capacitive elements 14a-14d to retard the signal the inverse of phi6 by a prescribed time. The delayed control signal 17 is led to a 2-input CMOS NAND gate 16 together with the signal the inverse of phi6, the gate output 18 is inverted via a CMOS inverter 19, to turn on/off an N-channel CMOSFET 21. The drain of the FET 21 is connected to a line 9 and the source is connected to a low potential line 6, the drain line 9 of the memory cell 1 (N-channel FAMOSFET) is discharged to quicken the read just after write.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an electrically writable semiconductor memory device composed of non-volatile memory cells such as FAMOS transistors on a semiconductor substrate, and particularly relates to a non-volatile memory device. The present invention relates to a semiconductor circuit device in which charges are removed from a drain line of a group of nonvolatile memory cells immediately after a write operation is completed in a circuit, so that a subsequent read operation can be performed quickly.

[Conventional technology]

As a conventional electrically writable semiconductor memory device,
An EPROM using a FAMOS transistor as a nonvolatile memory cell will be explained with reference to FIG. 3 as an example.

FIG. 3 is a circuit diagram of a write/read section of one memory cell constituting this type of EPROM.

In the same figure, 1 is an N-channel type F as a memory cell.
AMOS transistor (hereinafter abbreviated as FAMOS)
, 2, 3.4 and 5 are N-channel type MOS transistors, and 6 is a low potential source.
source is connected.

The FAMOSi and MOS transistors 2, 3 and 4 are connected in series, and the drain side of the MOS transistor 4 is connected to a sense amplifier (not shown) through an output line 7. Also, N-channel type M
O8) The source of the run raster 50 is connected to the connection point between the drain of the MOS transistor 3 and the source of the MOS transistor 4, and its drain is connected to the first high potential source 8. In addition, 9 is an N-channel type FA
A drain line is shown in which the drain of MOS 1 is connected to the source side of MOS transistor 2 in the upper stage.

Next, the operation of the above circuit will be explained.

First, in the write state, the control signal φ1 is set to a low potential level rLJ, and the control signal φ5 is set to a high potential level “H”. Here, each control signal φ2. φ3 and φ4
When both become rH, the drain line 9 of the memory cell FAMOS 1 becomes a high voltage, and writing is performed in the FAMOS 1 by the commonly known avalanche injection.

Next, for reading, the control signal φl is set to “H”, and the control signal φ
5 to "L", and each control signal φ2. This is done by setting φ3 and φ4 to “H”. At this time,
If FAMOSI is written, FAMOSI is in the OFF state, so a potential determined by the sense amplifier (“H” side) appears on the output line 7, and if FAMOSI is not written, FAMOSI is in the ON state. Therefore, output line 7
There is a sense amplifier and each FAMO8i.

The potential determined by MOS transistors 2 and 3 (“L”
side) appears.

By the way, consider a case where it is not desired to write to FAMOS1 in the write state. At this time, control signal φ4 is set to rLJ.
You can leave it as the drain line 9 of FAMOS1.
is in a state where a high voltage is applied. Therefore, when the state changes from writing to reading, FAMOS 1 turns on,
It works to pull out the high potential stain on the drain line 9 and bring the output line 7 to the rLJ level.

[Problem that the invention seeks to solve]

However, since the conventional device is configured as described above, when the FAMOS as a memory cell changes from the write state to the read state, it is necessary to discharge the drain line of the FAMOS.

Therefore, there is a problem in that a read operation immediately after writing is delayed.

This invention was made to solve the above problems, and by providing a circuit that discharges the drain line of a memory cell immediately after writing, a semiconductor circuit device that can quickly perform a read operation immediately after writing is provided. The purpose is to provide.

[Means for solving problems]

The semiconductor circuit device according to the present invention is an electrically writable semiconductor memory device configured with nonvolatile memory cells on a semiconductor substrate, and includes a MOS transistor connected in parallel to the nonvolatile memory cells, and a MOS transistor connected in parallel to the nonvolatile memory cells. A drive circuit configured to conduct the MOS transistor for a certain period of time immediately after writing to the memory cell is provided, and the drive circuit conducts the MOS transistor to discharge the charge on the drain line of the nonvolatile memory cell. This is how it was done.

[Effect]

The semiconductor circuit device according to the present invention can quickly discharge charges remaining after writing to the drain line of a nonvolatile memory cell such as FAMOS, and thus can quickly perform a read operation immediately after writing.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor circuit device according to the present invention. In Figure 1, parts equivalent to the third prisoner are given the same reference numerals, and the FA constituting EPR0M
The MOSI write and read circuit sections are the same as in the conventional example. 10 receives the write control signal φ6 associated with the write operation of FAMOSi as an input signal.
This delay circuit 10 is a CMO8 type delay circuit that delays the CMOS inverter 11 by a certain period of time.
N-channel, P-channel type MO paired with a to 11e
Gates 13m and 13b consisting of S transistors 12a and 12b, and capacitor elements 148 to 14d
It is composed of. Reference numeral 16 denotes a two-manufactured CMOS NAND ( N
19 is a CMOS inverter that receives the NAND output obtained from the output line 18 of this NAND gate 16, and 21 is an N-channel type that is driven on and off by the inverted output obtained from the output line 20 of this inverter 19. This MOS transistor 21 has its drain connected to the drain line 9 of FAMOSI, and its source connected to the low potential source 6, and is driven based on the inverted output to connect the drain line of FAMOSI. It is designed to discharge 9 charges.

Note that 15 is a second high potential source, which is set to be at a low potential during writing and at the same potential during reading as the first high potential source 8. The operation of the example configuration will be explained with reference to FIG. Here, the writing and reading operations to the FAMOS 1 are the same as those in the conventional example described above, and therefore will be omitted. here,
A case in which writing to the N-channel FAMOS 1 is not desired will be described. In writing, the pulse shown in FIG.
These signals are respectively input to the human-powered CMOS NAND gates 16, and when this signal φ6 is "L", a write operation is performed. When the signal φ6 rises from rLJ to rHJ, the output waveform shown in FIG. 2(b) appears on the output line 1T after passing through the delay circuit 10. As a result, Nand Gate 16
After passing through the CMOS inverter 19, an output waveform shown in FIG. 2(e) appears on the output line 20.

As a result, the N-channel O8 transistor 21 is turned on only during the rHJ period of the output of the signal waveform inverter 19 shown in FIG.
The charge on the drain line 9 is discharged. At this time, rH of the output of the inverter 19 shown in FIG. 2(e)
At the J level, the signal φ6 rises from "L" to rHJ. That is, since it occurs only immediately after writing, it has no effect on writing and reading.

Therefore, the charge on the drain line 9 of the FAMOS 1 is immediately discharged by the N-channel O8l-transistor 21 immediately after writing, so that the output line 17 immediately becomes the rLJ level during reading.

Note that the present invention is not limited to the above embodiments (
Any circuit may be used to drive the N-channel MOS transistor 21 connected in parallel to the FAMOS 1.
In short, as is clear from the signal waveform in FIG. 2, any device that detects the rising edge of the write signal and generates a pulse of a constant width is sufficient.

In addition, although the above example shows the case of EPROM using FAMOS, FAMOS is also used as a nonvolatile memory cell.
It is also possible to use a type other than S, and the present invention can be applied to all electrically writable semiconductor memory devices in which it is necessary to discharge the drain line of a memory cell group in which these memory cells are arbitrarily arranged.

〔Effect of the invention〕

As described above, according to the present invention, since the drain line of the nonvolatile memory cell is discharged immediately after writing, there is an effect that the read operation immediately after writing can be performed quickly.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing a semiconductor circuit device according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram used for the operation of the above embodiment, and FIG. 3 is a circuit configuration diagram showing a conventional example. . 1...-N channel type FAMOS, 2-5...N
Channel type MOS transistor, 6 φ low potential source,
7...-output line, 8... first high potential source, 911
・-- Drain line, 10 fists --- CMO8 type delay circuit, tia ~ lie, 19 -, -, CMOS
Inverter, 131, 13b@a * *geh, 14
a to 14d-...Capacitive element, 15.-〇.Second high potential source, 16.ψ.-CMOS NAND gate, 17, 18
．． 20 -...Output line, 21-...-N channel type M
OS transistor.

Claims (3)

[Claims] (1) In an electrically writable semiconductor memory device configured with nonvolatile memory cells on a semiconductor substrate, a MOS transistor connected in parallel to the nonvolatile memory cell and a MOS transistor immediately after writing to the nonvolatile memory cell are connected. A drive circuit configured to conduct the MOS transistor for a certain period of time is provided, and the drive circuit conducts the MOS transistor to discharge the charge on the drain line of the nonvolatile memory cell. Characteristic semiconductor circuit device. (2) The drive circuit includes a CMOS type delay circuit that receives a write control signal related to a write operation of a nonvolatile memory cell as an input signal and delays the control signal for a certain period of time, and an output signal of this delay circuit and the write control signal related to the write operation of the nonvolatile memory cell. Control signal input 2
2. The semiconductor circuit device according to claim 1, comprising an input CMOS type NAND gate, and a MOS transistor is driven based on the output of the NAND gate. (3) The semiconductor circuit device according to claim 1 or 2, wherein the nonvolatile memory cells are comprised of FAMOS transistors.