JPS6061995A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain an EPROM which can accelerate a chip enable access without impairing the collation function during a write mode and also after the write mode, by lowering the bit line potential after the end of writing down to the same level as the bit line potential during a read mode. CONSTITUTION:An n-channel transistor TR8 constituting a circuit which holds the value equal to the voltage in a read mode between the source and the earth of a TR4 for chip enable use of an EPROM. The gate of the TR8 is connected to a drain to actuate a diode. In a data collation mode after writing, the TR4 is turned on and a bit line BL is set at a low potential since a chip enable signal CE is set at L level. Under such conditions, the potential of the line BL is higher than an earth potential by an amoung equivalent to the threshold voltage VTH of the TR8. The potential of the line BL is approximately equal to the voltage VTH in a chip non-selection mode. Thus the chip enable access time can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION The present invention relates to improvements in semiconductor memory devices, and more particularly to electrically programmable read-only memories. The electrically writable read-only memory referred to here is EPROM (elect).
Programmable Read Ot
blyMemory),! :, E”PROM(E
electrical EragableProgram
(mable read only memory), and hereinafter collectively referred to as EPROM.

[Technical background of the invention and its problems]

As the amount of information increases, the capacity of memory is increasing, and this increase in memory capacity requires a large number of memory cells, which in turn requires the use of bit lines and word lines for selecting memory cells. This results in an increase in parasitic capacitance. An increase in parasitic capacitance causes a delay in address access time, and in the case of EPROMs, the bit line potential must be lowered to a low potential to prevent erroneous writing when verifying the written data after writing data to the memory cell. The reason for this is that the potential of the bit line remains at a high potential (write potential) after data is written, so when verifying the written data, it is judged as if the data had been written. This is because there is a risk that data may be written erroneously when writing to a primary 0 memory cell.

Lowering the potential to such a low potential will result in a delay in chip enable access time.

Here, an example of a conventional EPROM is shown in FIG. 1st
In the figure, 1 is an n-channel FE for data writing.
T (hereinafter referred to as a write transistor), the write data Din is applied to its gate, and the write voltage is applied to its drain.

The source of write transistor 1 is an n-channel FET.
The drain of a transfer gate 2 consisting of
It constitutes L.

The drain of an n-channel type memory cell transistor (hereinafter referred to as a memory cell) 3 having a floating gate is connected to the bit line BL. The word line WL is connected to the gate of the memory cell 3, and the source is grounded. A chip enable signal CF is input to the gate of the chip enable transistor 4 via an inverter 5. The logic of this chip enable signal α is shown in the state at the external input terminal (FIG. 2), and the input level of the gate of the transistor 5 is assumed to be the same as the logic at this external input. On the other hand, a sense amplifier 7 is connected to a connection point between the source of the write transistor 1 and the drain of the transfer gate 2 to take out an output. Reference numeral 6 designates a transistor that acts as a load for the memory cell 3. Preferably, an intrinsic type transistor is used because it can suppress the voltage drop due to the threshold voltage of the transistor and operate at a high level. .

Next, the operation will be explained (see Fig. 2). First, address A
dd is set, and then the output enable signal OE becomes 'H.
', the chip enable signal CF becomes H', and the output pin Dout becomes a high impedance state Hi-Z. Next, the write voltage Vflp is applied, and the input bin Din
When data is input, the chip enable signal CE becomes %.
When LI is reached, embedding is performed for a time T1. Next, when the chip enable signal CE is set to %HI again, the 1st column decode signal CD and the word line WL17'l signal become %L.
Since the memory cell 3 is not selected and the transistor 4 is turned on, the bit line BL is at a low potential (nearly the ground potential). Here, the bit line BL is set to a low potential after writing.

This is because if the potential of the bit line is maintained at a high potential, there is a risk that the data may be erroneously written during data verification after writing. Next, both the output enable signal section and the chip enable signal CE are set to %L.
1, and by reading the data, it is compared with the written data.

In this way, conventionally, the chip enable signal CE input In
' (This means non-selection during a read operation), the potential of the bit line IjL is set to approximately the ground potential, but this causes a delay in chip enable access in the read mode. In other words, during normal reading, the voltage ranges from approximately 1V (when the memory cell is not written) to 2V (when the memory cell is written).
(Fig. 3, solid line), whereas when performing selection operation from non-selection by chip enable signal CE,
This is because the voltage swings from v to 2v (dashed line in FIG. 3), which delays chip enable access.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor memory device that can speed up chip enable access without impairing write and post-write verification functions.

[Summary of the invention]

In order to achieve the above object, the EFROM according to the present invention has the following features:
The feature is that the bit line potential after writing is lowered to a potential equal to the bit line potential during normal reading. By doing so, it is possible to shorten the time for boosting the potential at the time of chip enable, thereby speeding up chip enable access.

[Embodiments of the invention]

An embodiment of an EPROM according to the present invention will be described below with reference to the drawings.

FIG. 4 shows an embodiment of an EPROM according to the present invention. In Fig. 4, the same or overlapping parts as in Fig. 1 are given the same reference numerals, and their explanations will be omitted.

The structure of Figure 4 is different from Figure 1 of the middle part.
An n-channel transistor 8 is inserted between the source of the A4Tn transistor 4 and the ground, which constitutes a circuit that maintains the voltage at a value equal to the read voltage. The gate of this transistor 8 is connected to the drain so that it operates as a diode.

Now, with such a configuration, writing and reading operations are the same as before and there is no change. However, when verifying data after writing, T! Since the chip enable signal CE is SL" for a period of time, the transistor 4 is turned on and the bit line BL is at a low potential. The threshold voltage N1 of the transistor 8 becomes higher than the ground potential by an amount of V.H (=0.8V).Also, when the chip is not selected, the bit line B
The potential of L also becomes approximately the threshold voltage VTII. Therefore, the characteristics are similar to those shown by the solid line in FIG. 3, and the chip enable access time can be shortened.

Next, FIG. 5 shows another embodiment. In this example, a diode 9 is used in place of the transistor 8 in FIG. 4, and in this case as well, the potential of the bit line when the chip is not selected is the forward voltage of the diode 90 UF (-=0.8V). be able to.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to increase the speed of chip enable access while maintaining the % write and post-input verification functions as before.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of the circuit configuration of a conventional EPROM. FIG. 2 is a timing chart for explaining the operation of each part, and FIG. 3 is an explanatory diagram of chip enable access time. FIG. 4 is a circuit diagram showing an embodiment of the EPROM according to the present invention. FIG. 5 is a circuit diagram showing another embodiment. DESCRIPTION OF SYMBOLS 1... Writing transistor, 2... Transfer gate), 3... Memory cell transistor, 4... Chip enable transistor 8... Voltage holding transistor, 9... Voltage holding diode . Applicant's agent Kiyoshi Inomata

Claims (1)

[Scope of Claims] 1. In an electrically writable read-only memory device, the potential of the bit line corresponding to the memory cell after data has been written to the memory cell or when a chip is not selected is determined by the bit line when reading. A semiconductor memory device comprising a voltage holding circuit that holds a voltage at a value substantially equal to a potential. 2. A semiconductor memory device according to claim 1, wherein the voltage holding circuit is a transistor inserted in series between the memory cell and ground and connected with a self-bias. 3. In the device according to claim 1. In semiconductor memory devices, the voltage holding circuit is a diode forward connected between the memory cell and ground.