JPS62214451A - Storage device control system - Google Patents

Abstract

PURPOSE:To shorten the processing time by selecting plural storage devices simultaneously when a simultaneous designation mode signal is sent and writing the same information in all storage devices simultaneously by one write instruction from a host device. CONSTITUTION:A mode designating part 4 consists of an AND circuit 41 and an FF 42, and the circuit 41 operates AND between a write designation signal from a CPU 2 and a simultaneous selection mode indicating signal from a storage device control part 3. The FF 42 sets the output terminal Q to '1' if simultaneous write designation is indicated, and the FF 42 sets the terminal Q to '0' if this designation is released, and a simultaneous selecting part 5 selects storages devices 1(0)-1(n) simultaneously when receiving the simultaneous selection mode signal from the designating part 4.

Description

[Detailed Description of the Invention] [Summary] A storage device control method in a data processing system having a plurality of storage devices, in which write processing for the plurality of storage devices is serially processed for each storage device. On the other hand, when a simultaneous designation mode signal is sent, the plurality of storage devices are simultaneously selected, and the same information is simultaneously written to all the storage devices with one write command from the host device. By doing so, it becomes possible to shorten the time required for writing the same information.

[Utilization field of industry positive]

The present invention relates to a storage device control method in a data processing system having a plurality of storage devices.

Normally, in a data processing system having a storage device, when the data processing system starts operating, information is written to confirm the operation of the storage device and processing to clear the stored contents is performed.

On the other hand, due to recent advances in large-scale integrated circuit technology, the storage capacity of the storage devices used has increased, and the time required for writing and clearing information has accordingly increased.

There is a need to put into practical use a storage device control system that can efficiently perform such information writing and clearing processing.

[Conventional technology]

FIG. 3 shows a block diagram illustrating a conventional example.

Storage devices 1(O) to 1(3) shown in FIG. 3 are 8096 word x 8 bit storage devices (for example, memory (1?AM)).
The example is the case where four are used.

The central processing unit (hereinafter referred to as CPU) 2 receives a clock signal (input to terminal CLK) sent from the clock generator 6.
The address signal AO is operated based on the address signal AO and sent from terminal A.
-A15 specifies a plurality of storage devices 1(o) to 1(3) and instructs them to write information.

To address signal 〇-A15, the upper three digits of address signals A13 to A15 are converted by the storage device control unit 3 to become chip select signals CS for each storage device 1(0) to 1(3). Specify one access from (O) to 1(3). Also, the address signal AO-At2
specifies an address within each storage device 1(0) to 1(3).

Note that the terminal W of the CPU 2 is a terminal for sending out a write designation signal, and this signal becomes a write enable signal WE on each of the storage devices 1(0) to 1(3). Also, terminal E is CPU2
The enable signal terminal outputted from the terminal means a terminal for transmitting write information Do-07 (8-bit information fIa).

For example, when performing the same information filling and clearing processing for each storage device 1(0) to 1(3), each storage device 1(o) to
1(3) and its address are specified, and write processing is executed for the specified storage devices 1(0) to 1(3).

That is, for example, when writing the same information to the storage device 1(0), the CPU 2 sends address signals AI3 to A15 (input to terminals A-C of the storage device control section 3) to the storage device control section 3.
to specify the storage device 1(o).

At the same time, the memory device 1 (
0), and write the same information Do-07 to the specified address using the write enable signal.

This is repeated in sequence for all addresses of each storage device 1(0) to 1(3), and each storage device 1(o) to
1(3), if the same information was written, clear processing was performed. Note that the clearing process means writing the information "oooooooo" and setting all the contents of the storage device to "0".

[Problem that the invention seeks to solve]

As mentioned above, the clearing process is performed when the information “111111” is cleared, for example.
11” is written, the information “oo
Clearing is performed by writing "oooooo".

However, the conventional write process for clearing is
(0) to 1(3) are serially cleared one by one, so as the system storage capacity increases, the processing time also increases (the processing time is the sum of the storage capacity). There was a problem in that it was proportional to (proportional to).

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the invention in detail.

The block diagram of this principle shown in FIG. 1 includes a storage device group 1 consisting of a plurality of storage devices 1(o) to 1(n) that store information, and a storage device group 1 that instructs writing/reading of information to the storage device group 1. a central processing unit 2; a storage device control unit 3 that controls execution of information occupancy/continued processing operations of the storage device group 1 according to instructions from the central processing unit 2; Storage device 1 (0
) to 1(n) at the same time. When a simultaneous selection mode signal is received from the mode specifying means (mode specifying section) 4, each memory is It is composed of simultaneous selection means (simultaneous selection section) 5 for simultaneously selecting devices 1(0) to 1(n).

[Effect]

When a simultaneous designation mode signal is sent from the mode designation means (mode designation section) to the simultaneous selection means (simultaneous selection section), the plurality of storage devices are selected simultaneously, and one
The same information can be written to all storage devices with a single write command, for example “
By writing the "oooooooooo" information at the same time, it is possible to shorten the time required for the input processing operation for the same information.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 2 shows a block diagram illustrating the invention in detail. Note that the same reference numerals indicate the same objects throughout the figures.

In this embodiment as well, four storage devices (for example, memory (RAM)) 1 (O
) to 1(3) will be taken as an example.

The mode designation unit 4 of this embodiment includes an AND circuit 41 that takes a logical product condition of the simultaneous selection mode designation signal output from the terminal 6 of the storage device control unit 3 and the write designation signal output from the terminal W of the CPU 2. When simultaneous writing is specified from CPU2, that is, C
When the data Do from PU2 is “1” and the simultaneous selection mode instruction signal and the write specification signal are on at the same time,
Clock terminal CK turns on and its output terminal Q becomes “1”
In addition, when the simultaneous write designation is canceled from the CPU 2, that is, when the data Do from the CPU 2 is "0" and the simultaneous selection mode instruction signal and the write designation signal are on at the same time, the output A flip-flop (hereinafter referred to as FP) configured to set the terminal Q to "0"
It consists of 42.

Further, the simultaneous selection section 5 includes two NOT circuits 51, 52, one NANI) circuit 53 and each storage device 1(0) to 1(3).
) OR circuits 54 (0) to 5 provided corresponding to
4 (3).

The storage device control unit 3 consists of a decoder, and the CPU 2
It decodes the combination of address signals ^13 to A15 output from the CPU 2 and outputs pulses synchronized with the enable signal amount from the CPU 2 to the output terminals O to 7.

Note that the outputs of the output terminals θ~3 are connected to the respective storage devices 1 (0
) to 1(3), terminal 6 is used to select FF 42 for specifying whether or not to perform simultaneous writing, and terminals 4, 5 and 7 are unused in this embodiment.

Normally, the output terminal Q of the FF 42 is "0" (ie, "low level"), so the output of the NAND circuit 53 is 1" (ie, 'high level').

Therefore, for example, address signal A15 = A14 = AI
When 3=“0”, storage device 1 (0), address signal A1
When 5=^14="O" and A13="1", storage device 1 (1) is selected, and information DO to D7 is written to each.

Next, when simultaneous writing is designated by the CPU 2, the data DO becomes "1" and at the same time, the output terminal 6 also becomes "1" due to decoding by the storage device control unit 3, and the output terminal Q of the FF 42 becomes "1".

In this state, for example, the information Do to D to the storage device 1(0)
7 is specified, the output of the NAND circuit 53 becomes “0” at the same timing as the output terminal 0 of the storage device control unit 3.
” becomes.

The output of this NAND circuit 53 is the OR circuit 54 (0)
~54(3) to the chip select terminals C8 of the storage devices 1(0) to 1(3), and together with the write enable signal amount, the information DO to D7 to the storage devices 1(0)
At the same time as writing, the same information Do to D7 is written to all of the other memory bags H1(1) to H1(3).

Therefore, in order to clear the memory devices 1(0) to 1(3), after setting the output terminal Q of the FF 42 to "1", write all "0" information to the memory device 1(0). All you have to do is to do this, and the clear processing time can be significantly shortened.

In the above description of this embodiment, the clearing process was explained, but the information Do-07 that enters the storage device 1(0) may be of any kind.It is also very effective in the write test that is generally performed when the CPU 2 is released from reset. is obtained.

In addition, in this embodiment, a storage device of 8096 words x 8 bits is used.
Although an example using a number of bits has been described, there is no limit to the storage capacity, bit configuration, or number of bits, and the larger the number of bits written at the same time, the greater the effect will be.

〔Effect of the invention〕

According to the present invention as described above, it is possible to simultaneously write the same information to all storage devices with a single write command from the CPU, so when writing the same information to multiple storage devices, the information write This has the effect of shortening the processing time.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, and FIG. 3 is a block diagram explaining a conventional example. In the figure, 1 is a storage device group, 1(0) to 1(n) are storage devices, 2 is a CPU, 3 is a storage device control unit, 4 is a mode specifying unit, 5 is a simultaneous selection unit, and 6 is a clock generation unit , 41 is an AND circuit, 42 is FF151, 52 cN
OT times m, 53 indicates a NAND circuit, and 54 (0) to 54 (3) indicate an OR circuit, respectively.

Claims (1)

[Claims] A storage device group (1) consisting of a plurality of storage devices (1(0) to 1(n)), and instructions to write/read information to the storage device group (1). a central processing unit (2) that
A data processing system comprising: a storage device control unit (3) that controls information writing/reading operations of the storage device group (1) according to instructions from the central processing unit (2); a mode specifying means (4) for specifying a simultaneous selection mode in which the plurality of storage devices (1(0) to 1(n)) are selected simultaneously according to a command from the mode specifying means (4); and a simultaneous selection mode signal from the mode specifying means (4). simultaneous selection means (5) for simultaneously selecting the plurality of storage devices (1(0) to 1(n)) when receiving a message; When the simultaneous selection mode signal from (4) is sent to the simultaneous selection means (5), one write command from the central processing unit (2) causes the plurality of storage devices (1(0) to 1(n
)) is a storage device control method characterized by performing simultaneous write operations.