JPS6221412B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high sensitivity amplifier that is controlled by two-phase clock signals and functions as a differential amplifier or comparator. A normal differential amplifier has a unique input offset, and unless a differential signal greater than this offset is input, it cannot be detected as a signal.

The present invention provides a high-sensitivity amplifier that uses a novel signal input method to amplify differential signal voltages and can sufficiently detect differential inputs even at levels below the input offset unique to differential amplifiers. That is.

The high sensitivity amplifier of the present invention includes first and second input terminals, first and fourth transistors connected to the first input terminal, and second and third transistors connected to the second input terminal. a transistor, first and second capacitors, and a differential amplifier, the other ends of the first and third transistors are connected to each other and to the first capacitor,
The other ends of the second and fourth transistors are connected to each other and to a second capacitor, and the other ends of the first and second capacitors are connected to the first and second inputs of the differential amplifier, respectively. the gates of the first and second transistors are driven by a first clock signal, and the gates of the third and fourth transistors are driven by a second clock signal that does not overlap with the first clock signal. The differential amplifier is driven by a signal, and the first and second input points of the differential amplifier are biased to a constant potential while the third and fourth transistors are conductive. It is something to do.

Hereinafter, an example of the implementation of the present invention will be specifically described with reference to the drawings to help understand the present invention.

FIG. 1 shows an embodiment of the present invention. For convenience, the six transistors shown in the figure are n-channel transistors.
I will proceed with the discussion assuming that it is a MOS transistor, but
The invention is not limited thereto. Transistors 1, 3, 5 and transistors 2, 4, 2 are connected to the first and second input terminals IN, respectively.
6 are connected, and the output points G and D of the input section are connected to the input points of the differential amplifiers S and A, respectively. A first input terminal IN is connected to transistors 1 and 4, and a second input terminal is connected to transistors 2 and 3. first transistor 1
The other ends of the third transistor 3 and the third transistor 3 are connected at a point A, and further connected to one end of the first capacitor _C1 . The other ends of the second transistor 2 and the fourth transistor 4 are connected at point B and further connected to one end of the second capacitor _C2 . The other ends of the first and second capacitors C ₁ and C ₂ are respectively connected to the first and second input points G and D of the differential amplifier S·A. The first input point G is connected to the power supply potential V _R via the transistor 5, and while the third transistor is conductive, the first input point G
is biased to a constant potential _VR . The second input point D is connected to the power supply potential V _R ' via the transistor 6, and while the fourth transistor is conductive, the second input point D is biased to a constant potential V _R '. Although the power supply potentials V _R and V _R ' may be the same, they are marked separately for correspondence with FIG. 3.

The first clock signal φ1 is input to the gates of the first and second transistors 1 and 2, and the first clock signal _φ1 is input to the gates of the third and fourth transistors 3 and 4 and the bias control transistors 5 and 6. A second clock signal _φ2 that does not overlap with the first clock signal _φ1 is input.

The circuit operation of FIG. 1 will be explained using the signal waveforms of FIG. 2. First, at time _t1, clock signal _φ2 is +5V
Then, transistors 3, 4, 5, and 6 become conductive, so the potentials V A , V _G , V B , and V D at points _A , G, _B , and _D corresponding to the electrodes of capacitors C ₁ and C ₂ are respectively V _IN , V _R , V _IN , V _R '.

Next, at time _t3, when the clock signal _φ1 becomes +5V, transistors 1 and 2 become conductive, and V _A and V _B become V _IN and V _IN , respectively.

Input points G and D of the differential amplifier S.A are in a floating state when transistors 5 and 6 are not conductive. Further, C ₁ and C ₂ are selected so that the parasitic capacitance of input points G and D is much smaller than the capacitance values of the first and second capacitors C ₁ and C ₂ . Therefore, at time _t3 , when V _A changes from V _IN to V _IN , V _G changes from VR to _{VR +} (V _IN - V _IN ). Similarly, when V _B changes from V _IN to V _IN at time t ₃ , V _D changes to V _R ' ¹ + (V _IN - V _IN ).
For the sake of simplicity, let's proceed by assuming that V _R =V _R ' ^1. After all, at time _t4 , the differential voltage V _GD between the input voltages V _G and V _D of the differential amplifier S.A. is |V _IN -V _IN ｜
×2, which is twice the differential voltage between the original input signals V _IN and V _IN . first and second input points G,
Assuming that the parasitic capacitance value at point D is _CP and the capacitance values of the first and second capacitors C ₁ and C ₂ are C, the exact formula is V _GD = |V _IN −V _IN |×2× C÷(C+C _P ) (1). Therefore, for C _P <<C, V _GD =2×|V _IN
−V _IN |. Furthermore, in order for equation (1) to hold true, it is necessary that the input signals V _IN and V _IN do not change from time t ₁ to t ₄ . This means that V _IN and V _IN are
It may be output from a low impedance signal source or a large capacity capacitor.

Therefore, as long as .
It is possible to multiply the differential voltage by 2 ⁿ times by cascading stages.

FIG. 3 shows an example of a specific circuit of the differential amplifier S.A in FIG. 1, including a bias control transistor 5,
6, and the power supply potentials V _R , V
This is an example in which _R ' is obtained from the main body of the differential amplifier S.A. Transistors 7, 8 are transistors 1,
The transistors 9 and 10 are of the enhancement type, similar to transistors 2, 3, 4, 5, and 6, and the transistors 9 and 10 are of the depletion type. The transistors 7 and 8, 5 and 6, and 9 and 10 are designed to have substantially the same characteristics, and have a symmetrical structure as a whole. Transistors 9 and 7, 10 and 8 form an inverter, and the sources of transistors 7 and 8 are connected to a constant current source. transistors 7 and 8
The gates correspond to input points G and D in FIG. 1, respectively. The gates of transistors 9 and 10 are connected to their respective sources, and the output points out and out of the amplifier are connected to the respective sources.
It is becoming.

Transistors 5 and 6 control the connection of the drains and gates of transistors 7 and 8 by clock signal _φ2 , respectively.

When the clock signal _φ2 is +5V, the gates and drains of transistors 7 and 8 are shorted, respectively. That is, the input point and output point of the inverter made up of transistors 9 and 7 are short-circuited, and similarly the input point and output point of the inverter made up of transistors 10 and 8 are short-circuited.
Therefore, input points G and D are biased to a potential that provides the highest gain in the transfer characteristics of each inverter. The potentials at input points G and D will be equal if transistors 9 and 10 and 7 and 8 have exactly the same characteristics.

However, the threshold difference between transistors 7 and 8 is △
If there is only V _T , the bias potential between input points G and D will deviate by approximately ΔV _T , so the input offset of the differential amplifier due to the threshold difference ΔV _T is compensated for, and the effective input offset becomes extremely small. This input point G,
The bias level of D corresponds to the power supplies _VR and _VR ' in FIG. As explained above, by combining the circuits shown in FIGS. 1 and 3, for example, a differential amplifier having a much higher sensitivity than that of the conventional structure can be obtained.

[Brief explanation of the drawing]

FIG. 1 shows a high sensitivity amplifier as an embodiment of the present invention, in which the first and 22nd input terminals IN,
A four-terminal circuit whose output terminals are the first and second input points G and D of the differential amplifier S.A is connected to the input points G and D of the differential amplifier S.A. In the figure, 1, 2, 3, and 4 are the first, second, third, and fourth transistors, respectively, and C ₁ , C ₂
are the first and second capacitors, and φ ₁ , φ
₂ are first and second clock signals; 5,
6 is a transistor for bias control. Second
The figure is a waveform diagram showing the operation of the circuit of FIG. 1. FIG. 3 shows an example of a circuit suitable for use as a differential amplifier S.A, which is one of the components of the present invention. 5 and 6 in the figure correspond to 5 and 6 in FIG. 1, and are shown together for convenience. 7,
8 is an enhancement type transistor;
9 and 10 are depletion type transistors.

Claims (1)

[Claims] 1 first and second input terminals, first and fourth transistors connected to the first input terminal, second and third transistors connected to the second input terminal, and first and fourth transistors connected to the second input terminal; a second capacitor and a differential amplifier;
The other ends of the transistors are connected together and connected to a first capacitor, the other ends of the second and fourth transistors are connected together and connected to a second capacitor, and the other ends of the second and fourth transistors are connected together and connected to a second capacitor, and The other ends are connected to first and second input points of the differential amplifier, respectively, the gates of the first and second transistors are driven by a first clock signal, and the gates of the third and fourth transistors are driven by a first clock signal. The gates of the transistors are driven by a second clock signal that does not overlap with the first clock signal, and the first and second inputs of the differential amplifier are driven while the third and fourth transistors are conducting. A high-sensitivity amplifier characterized in that each point is biased to a constant potential.