JPH0361278B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated sense amplifier circuit for sensing differential voltages.

A conventional flip-flop type sense amplifier circuit that boosts voltage by capacitive coupling is shown in FIGS. 1a and 1b. This circuit includes transistors 1 and 2 constituting a flip-flop, transfer gates 3 and 4 for sampling the input, integrated capacitive elements 5 and 6 for voltage reduction, and a discharge transistor 7. ₁ samples the input signal voltage, and at the rising edge of clock φ _p , boosts the voltage through capacitive coupling, simultaneously turns on transistor 7, activates the flip-flop, and outputs the output voltage from nodes A and B to any output circuit. . In such a driving method, a difference in boost amount occurs due to the asymmetry of the capacitive element when boosting the voltage, which degrades sensitivity. At the same time, rapid discharge toward the common source point occurs at the same time as boosting, which also degrades sensitivity. There were some shortcomings. It is well known that the sensitivity of a flip-flop type amplifier circuit becomes higher as the discharge rate becomes slower.

SUMMARY OF THE INVENTION An object of the present invention is to provide a sense amplifier circuit which eliminates these conventional drawbacks and allows a low input offset voltage.

The sense amplifier circuit of the present invention includes at least a pair of transistors whose drains and gates are cross-coupled and whose sources are commonly connected, and a pair of transistors whose respective one is connected to an input terminal and the other is connected to the cross-coupled drain or gate. transfer gate,
a pair of integrated capacitor elements having one end connected to each of the cross-coupled coupling points and the other end commonly connected; and a first transistor discharging a common source point of the transistor pair;
and a second transistor, the transfer gate is driven by a first clock, and after the first clock is set to a low level, the first discharging transistor is driven by a second clock set to a high level. The third clock rising signal is applied to the common connection terminal of the integrated capacitive element pair and the second discharge transistor after the integrated capacitive element pair becomes conductive.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to drawings showing embodiments. 2a and 2b are circuit diagrams and clock timing diagrams showing one embodiment of the present invention. Transistors 1 and 2 have their drains and gates cross-coupled, and their sources commonly connected. The transfer gates 3 and 4 each have one end connected to the input terminal IN or the other end connected to the cross-coupling point. The integrated capacitive element pairs 5 and 6 each have one end connected to the cross-coupling point and the other ends commonly connected. Transistors 7 and 8 are connected to discharge a common source point. The driving method is to first apply clock φ1 to the gate electrodes of transfer gates 3 and 4,
Sample the input. Next, the clock φ2 is applied to the gate electrode of the discharge transistor 7 to activate the flip-flop and perform initial amplification. Next, a clock φ ₃ is applied to the gate electrode of the discharge transistor 8 and the common connection terminal of the integrated capacitor element,
At the rising edge of the clock, nodes A and B are boosted, and at the same time transistor 8 is made conductive, discharge is accelerated, further amplification is performed, and the low voltage side is discharged to ground potential.

Although the above explanation was made using an n-channel MOS circuit, the present invention is not limited to this.
A channel MOS circuit may also be used, in which case the polarity of the clock will be reversed. Furthermore, although the clock waveform is idealized for simplicity, the pulse width is determined by the circuit constants and is not a fixed value. For example, the pulse voltage value may be such that the low level is 0V and the high level is the power supply voltage, but it is not limited to this, and any level that can control the transistor to be conductive or nonconductive may be used. The mutual relationship between the clocks is such that φ ₁ and φ ₂ do not overlap and φ ₂ rises after φ ₁ goes to a low level, and φ ₂ and φ ₃ rise after φ ₂ rises. ₃ will stand up. It is also well known that the slower the rise time of the clocks φ ₂ and φ ₃ , the lower the input offset voltage will be.

If the detection amplifier circuit according to the present invention is used, the node voltage difference is sufficiently amplified in the initial amplification, so even if the low voltage side is high and the high voltage side is low due to variations in the integrated capacitance elements, the flip-flop is never reversed. Also, when boosting the voltage, the voltage between the gate and the source increases, and the node rapidly discharges, but since the node is initially amplified, there is no inversion operation.

As explained above, in a flip-flop type amplifier circuit that boosts voltage through capacitive coupling, the present invention reduces the input offset voltage due to the asymmetry of the circuit constants by driving at a timing that boosts the voltage after initial amplification. Can be made smaller.

[Brief explanation of drawings]

FIGS. 1a and 1b are a circuit diagram of a conventional sense amplifier circuit and its clock timing diagram. Figures 2a and 2b are a circuit diagram and a clock diagram of an embodiment of the present invention.
It's the timing. 1, 2...Cross-coupled transistor, 3, 4...
Input transfer gate, 5, 6... integrated capacitive element, 7, 8... discharge transistor.

Claims (1)

[Claims] 1. A pair of transistors whose drains and gates are cross-coupled at least, and whose sources are commonly connected; and a pair of transfer gates, each of which has one connected to an input terminal and the other connected to the cross-coupled drain or gate; A pair of integrated capacitive elements having one end connected to each of the cross-coupled coupling points and the other end commonly connected, and first and second transistors discharging a common source point of the transistor pair, After driving the first clock with the first clock and setting the first clock to a low level, the first discharging transistor is turned on by setting the second clock to a high level, and then the integrated capacitive element pair is turned on. 2. A detection amplification circuit characterized in that a rising signal of a third clock is applied to a common connection terminal of the transistor and the second discharge transistor.