JPS62212861A - Buffer control system - Google Patents

Abstract

PURPOSE:To attain buffer control by a simple control means by grasping respective registers with lines and rows and controlling the input and output of data to/form respective registers by control means corresponding to the lines and rows. CONSTITUTION:An adaptor 7 is constituted of an MPU 4, a buffer control part 8 and a buffer part 9. The buffer control part 8 is constituted of a line control part 81 for sending a line signal to an arithmetic part 83 for outputting control signals corresponding to plural registers constituting the buffer part 9, a row control part 82 for sending a row signal corresponding to the arithmetic part 83 and the arithmetic part for forming the control signals corresponding to respective registers by ORs of the line signals and the row signals. Consequently, buffer processing operation can be controlled by the simple control method through the simple control means.

Description

[Detailed Description of the Invention] [Summary] This is a buffer control method in a data processing system, in which when controlling a buffer that adjusts the flow of data, a control means is added to each register that makes up the buffer. By configuring the system so that each register is understood by row and column, and the control means corresponding to the first row and column is used to control the input and output of data to each register, buffer control can be performed using a simple control means. becomes.

[Industrial application field]

The present invention relates to a buffer control method in a data processing system.

For example, when data is transferred in a data block of a predetermined capacity, a data buffer may be provided to correct the transfer speed of the data block, and control of the data buffer becomes complex as the amount of data to be transferred increases. Therefore, the general trend is that the amount of hardware for data retention functions and control functions increases proportionally.

In such a case, it is desired to put into practical use a control system that causes less hardware damage even when the amount of data to be transferred increases, and that can control the data retention processing function in a simple state.

[Conventional technology]

FIG. 4 is a block diagram illustrating a conventional example, and FIG. 5 is a diagram illustrating the flow of data in a data processing system.

FIG. 5 is a system diagram showing data transfer between a central processing unit (hereinafter referred to as CPU) 1 that controls each functional block that makes up the system and a storage device 3 that stores various data. Yes, the data flow during this period is adjusted/
An adapter 2 is provided for control.

The adapter 2 is connected to a data bus (a) (for example, 3
A buffer section 5 that adjusts the flow of data when transferring data from the 2-bit data bus (2-bit data bus) to the data bus (b) (for example, 8-bit data bus) that transports data to and from the storage device 3; , a buffer control unit 5' that controls the processing operation of the buffer unit 5, a buffer unit 6 that adjusts the flow of data when transferring data from (in the data bus) to the data bus (a), and processing of the buffer unit 6. It consists of a buffer control section 6' that controls the operation.

For example, the configurations of the buffer units 5, 6 and buffer control units 5', 6' when the data block is 16 bytes of data are shown in FIGS. 4(A) and 4(B), respectively.

FIG. 4(A) shows a case where a data block flows from a 32-bit data bus (a) to an 8-bit data bus (bl), and four registers A1 to A4. B1~B4.C1~C4,D1~
Register section 55 (0) to 55 (3) having D4
and each register ^1~A4.81~B4. C1-C4,
Control signals Φ~[
Flip-flop (hereinafter referred to as PF) that sends out phase]
1 to 16, and each register At to A4.81 to B4. C1-C4,1
) 1 to D4 and a multiplexer (hereinafter referred to as MPX) 57 that sends the latched data to the 8-bit data bus (b).

Incidentally, FIG. 4(B) shows the case where the data block flows from the 8-bit data bus (b) to the 32-bit data bus (a).

That is, in this example, registers At' to A4' and 81' to B4' process data in 1-byte units and latch input data in which 16 bytes constitute one data block.

Register sections 65 (0) to 65 (3) having C1' to C4' and Di' to D4', respectively, and register AI'
~A4', B1'~B4',CI' ~C
4'.

It is provided corresponding to DI '~D4', and MP performs the launch processing of each register section 65 (0)~65 (3).
FF1' to FF16' which send out control signals '' to [phase]' controlled by the instruction of L14, read the data latched in the register sections 65 (0) to 65 (3), and connect the 32-bit data bus. Driver sending to (a) (hereinafter referred to as DV) 67 (0) ~
67 (3).

The buffer unit 5 stores the data sent from the CPU in 32-bit units into each register unit 55 (0) to 55 (3
) registers A1-A4.81-84. C1~C4,D
Each register /ii ~A4.81~B4.I-04 is latched simultaneously and ruffed by 8 bits. C1~
Sequentially select from C4, DI to D4 with MPX57,
Send the selected data to the data bus (b).

Therefore, from FF9 to FF12, each register section 55 (0)
~55 FFI corresponding to (3) ~4. FF5~8. F
F9-12. Control signals that allow PFI3 to 16 to latch 32 bits of data at the same time ■~■, ■~■
, ■~@, ■~ [phase] is sent and controlled.

In addition, the buffer unit 6 stores the data sent from the storage device 3 in 8-bit units to each register unit 65 (0) to 65 (
3) Internal registers AI' to A4', Bl' to B4', C1
'~C4', DI'~D4' are latched, and each register section 65(0)~65(3) is latched to the corresponding DV67.
(0) ~ At each register section 65 (0) ~ 67 (3)
The 32 bits latched in 65(3) are simultaneously read out and sent to the data bus (a).

Therefore, each FFI'~PF16' receives control signals ■'~■', ■'~■', ■'~o', o' so that each register section 65(O)~65(3) can latch data.
~[Phase]' is fed and controlled.

[Problem that the invention seeks to solve]

In the buffer control method described above, data input/output is controlled in units of data blocks, which makes the control circuit complex, and as the capacity of the buffer increases, the amount of hardware for the control circuit also increases. There is a problem to be said.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the invention in detail.

The block diagram of FIG. 1 shows an outline of the configuration of an adapter 7 having the same functions as the adapter 2 described in FIG. 5, and the configuration includes an MPU 4 described in FIG. It is composed of a buffer section 9.

The buffer control unit 8 includes a row control unit (row control unit) 81 that sends a row signal to a calculation unit (operation unit) 83 that outputs a control signal corresponding to each of the plurality of registers constituting the buffer unit 9; Column control means (column control section) 82 that sends column signals to means (operation section) 83, and control signals corresponding to each register configuring buffer section 9 are created by ORing the row signal and column signal. It is composed of a calculation means (calculation section) 83.

[Effect]

When it is necessary to adjust the transfer speed during data transfer, the data buffer is made up of multiple registers that store data in units of 8 bits, and the multiple registers are understood in rows and columns to control the MPU. and row/column control means (
A control signal created by ORing the signals corresponding to the first row and column output from the row/column control unit) is output from the calculation means (calculation unit), and the control signal is used to input and output data to each register. By controlling the above, it becomes possible to control the buffer processing operation using a simple control means and a simple control method.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 1 to 3.

FIG. 2 is a block diagram explaining the present invention in detail, and FIG. 3 is a diagram explaining the operation of an embodiment of the present invention. In addition, the same reference numerals indicate the same objects throughout the figures.

This embodiment of the buffer section 9 shown in FIG. 2(A) shows a configuration diagram when used as a 16-byte data buffer, and FIG. 2(B) shows the row/column control section 8 of the buffer control section 8.
1.82 and the configuration of the calculation unit 83 are shown.

Register sections 55(0) to 55(3) shown in FIG. 2(A)
).

The MPX57 is the same as that explained in FIG. 4(A) (1).

The DV58 shown in FIG. 2(A) has a register section 55(0).
~55 (3) The data latched in (3) is sent to the 32-bit data bus (a), and qPx59 (
1) to 59(4) have a function of selecting and taking in data from the 8-bit data bus ('b) and data from the 32-bit data bus (a).

Furthermore, the register section 55 (0) to 55 (3) registers 81 to 4 of the content string. ..., Di-04 has front row registers Bl-B4. ..., DI~D4 and M
The outputs of PX59(1) to PX59(4) are connected.

The block diagram shown in FIG. 2(B) includes a row control unit 81 consisting of three 0FFI to FF3, a column control unit 82 consisting of four FFa to FFd, and an arithmetic unit 83 consisting of 12 OR circuits. A buffer control unit 8 consisting of
From the arithmetic unit 83, the register units 55 (0) to 55 (3)
Internal registers A1 to A4. ..., corresponding to DI to D4, and each register A1 to A4 . ..., D1~D
4 Control signal S^1 input manually to each clock terminal
~SA4, . . . , SD1 to SD4 are output.

In addition, to each register 1 to 4. ..., 01 to D4, when the clock terminal is "low", the state of the input terminal appears on the output side as it is, and when the clock terminal becomes "high",
This is an 8-via register that holds the state of the input terminal.

Further, the MPX 57 is a multiplexer having 4 input terminals and 1 output terminal, and sequentially selects four pieces of data (32 bit data) in units of 8 bit data and sends them to the 8 bit bus (b).

Next, for example, when starting data transfer from the 8-bit bus (bl) to the 32-bit bus (a), the MPU 4 transfers data from the 8-bit bus (bl) to the 32-bit bus (a).

Each FFI to FP3 in the column control unit 81.82. FFa-P
Fd is set to the reset state (state Li of (1) in FIG. 3(B)(a)), and each register A1 to A4. ..., D
Set I to D4 to the through state.

8-bit bus (bl to MPX59 (1) to 59
Data is input through (4), the FFI in the first row is set to the set state (state of (2) in (a) of FIG. 3(B)), and latching to register 81 is completed.

Next, in the 2nd byte, FF2 in the 2nd line is set (3rd
Figure (B) (a) (3) condition), 3 by 1 - 3
Fl on the row? 3 in the cent state (state (4) in (a) in Figure 3 (B)), and set state in which FFa in column a is set in the 4th byte (state (5) in (a) in Figure 3 (B)). state).

Thereafter, FFI to FF3 of the row control section 81 are returned to the reset state, and data transfer to the register section 55(0) corresponding to column a is completed. When the data transfer to the register section 55 (0) is completed, the register section 55 corresponding to columns b-d
Data is stored in each of (1) to register section 55 (3) under similar control.

Note that all the register sections 55(1) to 55(3)
), FFa in the column control unit 82
xFFd is in a set state (ie, "high" state B).

All register sections 55 (0) to register sections 55 (3
), the FFI in the row control unit 81
~FP3 reset state ((6) in (b) of Figure 3 (B)
) state) and register section 5 corresponding to FFa.
5 (0) is read by the DV58, sent to the 32-bit bus (a), and reset FFa to the state r4 (third
The state of (7) in (b) of figure (B), that is, "row 1 state S"
Make it.

When PFa is reset, the successive data of DV5B becomes the data of column b (FFb), and the data of column b (FFb)
When the output of data is completed, FFb is set to a "low" state. This is repeated in the same way for the 0th column (FFc) and the dth column (FPd), and when PFd becomes "low", all data has been sent to the 32-bit bus (al). The detailed operating situation described above is shown in FIG. 3(B).

Next, the data transfer process from the 32-bit data bus (al) to the 8-bit data bus (b) is shown in FIGS.
The explanation will be based on the time chart shown in (b).

32-bit bus (FFI to FP3.FFa-F in the control unit 81.82 in the 7th row and column when inputting data from al starts)
Reset all Fd in state B ((1) of (A) in Figure 3 (A))
) condition! ! E,) Toshi register 81-A4. ...
, D1 to D4 are put into a through state.

First, set FFa in column a to cent-like B (state of (2) in (a) of FIG. 3(A)), and latch data in the register section 55 (0) corresponding to FPa. Set the FFb of the column to the set state (the state of (3) in (a) of FIG. 3(A)) and set the register section 55 (1) corresponding to the FPb.
Latch data to .

Similar operations are set for FFc in column 0 and FFd in column d, data is latched in the corresponding register sections 55 (2) and 55 (3), and data transfer to buffer section 9 is completed. do. Note that at this point, FPI to FF3 of the row control unit 81 are in a reset state.

All register units 55 (0) to 55 of the buffer unit 9
When (3) is filled with data, all of the row control unit 81 (
7) FFI = FF3 position a < Figure 3 (A
) (7) (0) (6) state), and the data in the register AI in the register section 55 (0) corresponding to the FFI is set to M
Transfer to 8-bit path (b) via PX57 and FF
Let I be in the reset state (the state of (7) in (b) of FIG. 3(B)).

When the FFI is placed in the reset state, data transfer of the register 82 is started, and upon completion, the FF2 is placed in the reset state (state (8) in (b) of FIG. 3(B)).

This is repeated until the data transfer of register A4 is completed, and when the data transfer of register section 55 (0) is completed, FFa is set to the reset state (state 00 in (b) of FIG. 3(B)).

When FFa in column a is reset, the row control unit 8
With all FFIs to PF3 of 1 set in the set state, register section 55(1) of the following columns and register section 55(2 of column c) are set.
), the data transfer of the d column register section 55 (3) is repeated in the same manner as above, and all data are transferred to the 8-bit bus (b) via the side PX37.

〔Effect of the invention〕

According to the present invention as described above, even when the amount of data to be handled increases, buffer control can be performed using a simple control means and a simple control method.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining the operation in the embodiment of the present invention, and FIG. 4 is a conventional example. FIG. 5 is a block diagram explaining the flow of data in the data processing system. In the figure, 1 is CP[I, 2.7 is adapter, 3
is a storage device, and 4 is an MPU. 5.6.9 is a buffer section, 5', 6', and 8 are buffer control sections, 55 (0) to 55 (3) are register sections, 57.59
(1) ~ 59 (4) is MPX, 58.67 (0)
67(3) indicates a DV, 81 indicates a row control section, 82 indicates a column control section, and 83 indicates a calculation section. 6 mouth) Nopwo map (B) Shohanyuto jt! ``Child throat riff'' a rough diagram No. 46 (A) (υ

Claims (1)

[Scope of Claims] A data processing system comprising a data buffer means (9) for correcting a difference in data flow speed between constituent elements or an occurrence time of an event between the constituent elements, comprising: the data buffer means. (9) Buffer control unit (8) that controls data processing for multiple registers that make up
an arithmetic means (83) for generating a control signal for controlling data latch processing to the plurality of registers by ORing input row signals and column signals; and a processing section (83) for processing the row and column signals. Line control means (81) outputting under the control of 4)
and column control means (82), and the row signal and column control means (82) output from the row control means (81) and column control means (82) to control the data processing operation of the plurality of registers in the data buffer means (9). A buffer control method characterized by control based on column signals.