JPS6221138B2 - - Google Patents

Info

Publication number
JPS6221138B2
JPS6221138B2 JP57030326A JP3032682A JPS6221138B2 JP S6221138 B2 JPS6221138 B2 JP S6221138B2 JP 57030326 A JP57030326 A JP 57030326A JP 3032682 A JP3032682 A JP 3032682A JP S6221138 B2 JPS6221138 B2 JP S6221138B2
Authority
JP
Japan
Prior art keywords
function
input
output
register
macro
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57030326A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58146948A (ja
Inventor
Kenji Oomori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57030326A priority Critical patent/JPS58146948A/ja
Publication of JPS58146948A publication Critical patent/JPS58146948A/ja
Publication of JPS6221138B2 publication Critical patent/JPS6221138B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP57030326A 1982-02-26 1982-02-26 フアンクシヨンマクロ Granted JPS58146948A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57030326A JPS58146948A (ja) 1982-02-26 1982-02-26 フアンクシヨンマクロ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57030326A JPS58146948A (ja) 1982-02-26 1982-02-26 フアンクシヨンマクロ

Publications (2)

Publication Number Publication Date
JPS58146948A JPS58146948A (ja) 1983-09-01
JPS6221138B2 true JPS6221138B2 (enExample) 1987-05-11

Family

ID=12300681

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57030326A Granted JPS58146948A (ja) 1982-02-26 1982-02-26 フアンクシヨンマクロ

Country Status (1)

Country Link
JP (1) JPS58146948A (enExample)

Also Published As

Publication number Publication date
JPS58146948A (ja) 1983-09-01

Similar Documents

Publication Publication Date Title
US5594741A (en) Method for control of random test vector generation
US6016554A (en) Method for event-related functional testing of a microprocessor
US7769577B2 (en) Hardware accelerator with a single partition for latches and combinational logic
US7917348B2 (en) Method of switching external models in an automated system-on-chip integrated circuit design verification system
JPH06194415A (ja) 論理回路の試験方法とその装置
JPH0230056B2 (enExample)
US7483824B1 (en) Self-checking test generator for partially-modeled processors by propagating fuzzy states
US5859962A (en) Automated verification of digital design
US20060130029A1 (en) Programming language model generating apparatus for hardware verification, programming language model generating method for hardware verification, computer system, hardware simulation method, control program and computer-readable storage medium
CN101784905B (zh) 用于对片上系统的制造进行控制的设计信息的验证
US6144930A (en) Method for providing a memory model of a memory device for use in simulation
JPS6221138B2 (enExample)
US5245549A (en) Gate addressing system for logic simulation machine
WO2003021494A2 (en) Logic simulation
US20250363275A1 (en) Computer-Implemented Methods of Verifying a Processor Design Under Test, and Related Systems
US6339751B1 (en) Circuit design support apparatus and a method
US7441209B2 (en) Method, system and program product for providing a configuration specification language supporting error checking dials
JPH0345580B2 (enExample)
EP0231948A2 (en) Simulation system
JP2797128B2 (ja) 論理シミュレータ
JPH0429425Y2 (enExample)
JP2797127B2 (ja) 論理シミュレータ
JPH0443310B2 (enExample)
KR20050059985A (ko) 대용량메모리와 컴파일 회피를 이용한 하드웨어기반검증의 성능 향상 장치 및 이를 이용한 설계 검증 방법
JPS6235699B2 (enExample)