JPS62210618A - Manufacture of semiconductor element - Google Patents

Manufacture of semiconductor element

Info

Publication number
JPS62210618A
JPS62210618A JP5406386A JP5406386A JPS62210618A JP S62210618 A JPS62210618 A JP S62210618A JP 5406386 A JP5406386 A JP 5406386A JP 5406386 A JP5406386 A JP 5406386A JP S62210618 A JPS62210618 A JP S62210618A
Authority
JP
Japan
Prior art keywords
silicon
film
thin film
impurities
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5406386A
Other languages
Japanese (ja)
Inventor
Shinichiro Ishihara
伸一郎 石原
Ryuma Hirano
龍馬 平野
Takashi Hirao
孝 平尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP5406386A priority Critical patent/JPS62210618A/en
Publication of JPS62210618A publication Critical patent/JPS62210618A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To perform a diffusion process at lower temperature, by utilizing a difference in a thermal expansion factor among SiN or SiO2 and a substrate so that diffusion of impurities is promoted in a silicon thin film. CONSTITUTION:An amorphous silicon thin film 2 is formed on a substrate 1 of quarz glass, and glow discharge is generated with SiH4 and impurities serving as raw material gases to form an a-Si:H film containing impurities. A silicon nitride film 4 is formed by glow discharge with SiH4 and NH3 or N2 serving as raw material gas thereon, and the whole element is heated at about 450 deg.C to make boron in the a-Si:H film 3 be diffused into the silicon thin film 2. After selectively etching the silicon thin film 2, a silicon nitride film 6 is formed thereon, and the whole element is heated at about 450 deg.C to make oxygen in an oxidizing silicon film 5 be shallowly diffused into the silicon thin film 2. Diffusion of oxygen is promoted by stress due to difference in a thermal expansion factor among the silicon nitride film 6 and the substrate 1 and the like.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、基板上に集積された半導体素子の製造方法に
関する。さらに本発明は半導体素子の作成温度を低温化
させる製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing semiconductor elements integrated on a substrate. Furthermore, the present invention relates to a manufacturing method that lowers the manufacturing temperature of a semiconductor element.

従来の技術 従来例1.50気圧〜100気圧の水蒸気中でSLを酸
化させる技術がある。基板温度は600〜1000℃で
酸化速度は高速化され、酸化温度は低温化された。しか
し、50〜100気圧と非常な高圧であることや、基板
全体を高圧にしなければならないため大がかりな製造装
置となることが予想される。ウェハの直径が大きくなっ
ているため困難は増大する。また圧力を上げすぎるか、
温度を高くしすぎるとS s 02膜が逆に溶けてしま
う。
BACKGROUND ART Conventional Example 1. There is a technique of oxidizing SL in steam at 50 to 100 atmospheres. The substrate temperature was 600 to 1000°C, the oxidation rate was increased, and the oxidation temperature was lowered. However, since the pressure is extremely high at 50 to 100 atmospheres, and the entire substrate must be under high pressure, it is expected that the manufacturing equipment will be large-scale. Difficulties increase as wafer diameters increase. Or increase the pressure too much?
If the temperature is raised too high, the S s 02 film will melt.

従来例2.P2O5,B2O3等を溶剤に溶かして塗布
する方法も従来性なわれている。しかし不純物を拡散さ
せるためには従来から900 ’C以上の高温が必要で
あった。
Conventional example 2. A conventional method is to dissolve P2O5, B2O3, etc. in a solvent and apply it. However, in order to diffuse impurities, a high temperature of 900'C or higher has conventionally been required.

従来例3.ホウ素まだはリンを酸化ケイ素と有機バイン
ダとでディスク状に成形し、ウエノ・の片面にリンを含
むディスクを、もう片面にホウ素を含むディスクを並べ
て固定し、不純物を拡散する技術が従来からある。p型
とn型を同時に拡散するものである。しかし、この場合
は、ウェハの片面全面に同一の不純物しか拡散させるこ
とができなかった。かつ、拡散には高温を必要とした。
Conventional example 3. There is a conventional technology for diffusing impurities by molding phosphorus into a disk shape with silicon oxide and an organic binder, and fixing the disk containing phosphorus on one side of the boron and the disk containing boron on the other side. . This diffuses p-type and n-type at the same time. However, in this case, only the same impurity could be diffused over the entire surface of one side of the wafer. In addition, high temperatures were required for diffusion.

発明が解決しようとする問題点 半導体回路の集積化が進むとその工程では高温処理を避
けなければならない。不純物が相互拡散するからである
。微細化には是非低温プロセスが必要である。
Problems to be Solved by the Invention As the integration of semiconductor circuits progresses, high temperature processing must be avoided in the process. This is because impurities interdiffuse. A low-temperature process is absolutely necessary for miniaturization.

問題点を解決するための手段 本発明は、拡散源に不純物を含むa−8i:H(水素化
非晶質シリコン)膜を用い、これを選択エツチングして
必要な部分のみを残し、その上にチノ化シリコン(Si
N)膜または酸化シリコン(SiC2)膜等でカバーし
、S i N ゛ま/こはS 102と基板との熱膨張
係数の差もしくはさらに外部から機械的に圧力を加える
ものである。
Means for Solving the Problems The present invention uses an impurity-containing a-8i:H (hydrogenated amorphous silicon) film as a diffusion source, selectively etches it to leave only the necessary portions, and then Tinated silicon (Si)
The S102 film is covered with a silicon oxide (SiC2) film or a silicon oxide (SiC2) film.

作  用 本発明はこうした方法を用いることにより、不純物をシ
リコン薄膜中に拡散させることを促進させ、半導体プロ
セス中、最も高温を必要とする拡散プロセスを低温化さ
せることを可能とする。
By using such a method, the present invention promotes the diffusion of impurities into a silicon thin film, making it possible to lower the temperature of the diffusion process that requires the highest temperature among semiconductor processes.

実施例 以下、本発明による実施例をいくつかあげて説明する。Example Hereinafter, some embodiments according to the present invention will be described.

実施例 1 ここでは、シリコン薄膜を用いた薄膜トランジスタ(T
PT)の製造方法について述べる・第1図にその製造方
法の工程について述べる。
Example 1 Here, a thin film transistor (T
The manufacturing method of PT) will be described. The steps of the manufacturing method will be described in Figure 1.

表面を酸化させたシリコンウェハまたは、石英ガラスを
基板1とし、その上にLPGVDで、非晶質状のシリコ
ン薄膜2を形成する。原料ガスをS I H4−とじ、
真空度約0.5Torrで基板温度600〜630’C
で堆積する。堆積速度は約1八secであった。(第1
図(a)) 次に、13.56MHzの高周波によってSiH4と不
純物を原料ガスとしI Torr程度に保った状態でグ
ロー放電を発生させ、不純物を含むa−8i:H膜を形
成する。不純物としてはB2H6またはBF3を用いた
。S iH4に対して体積比10ppmから1o%程度
を用いた。シリコン薄膜2にドープするホウ素の量によ
って濃度およびa−3i:H膜厚を変化させた。ドープ
量によってTPTのしきい値電圧が制御できた。a−3
t:H膜厚は300〜10.000人を用いた。その上
にS I H4とNH3まだはN2を原料ガスとしてグ
ロー放電によってチッ化シリコン膜4を形成した。真空
度は約ITorrで、基板温度は180〜300℃とし
た。チツ化シリコン膜4を形成後、素子全体を450’
C程度に昇温し、a−3t:H膜3中のホウ素をシリコ
ン薄膜2に拡散させた。熱処理時間は5〜100分間と
しだ。(第1図(b))。
A silicon wafer or quartz glass with an oxidized surface is used as a substrate 1, and an amorphous silicon thin film 2 is formed thereon by LPGVD. The raw material gas is S I H4-bound,
Vacuum level approximately 0.5 Torr and substrate temperature 600-630'C
deposited in The deposition rate was about 18 seconds. (1st
(Figure (a)) Next, a glow discharge is generated using SiH4 and impurities as source gases with a high frequency of 13.56 MHz and maintained at about I Torr to form an a-8i:H film containing impurities. B2H6 or BF3 was used as an impurity. A volume ratio of about 10 ppm to 10% was used with respect to SiH4. The concentration and a-3i:H film thickness were varied depending on the amount of boron doped into the silicon thin film 2. The threshold voltage of TPT could be controlled by the doping amount. a-3
The thickness of t:H film was 300 to 10,000. A silicon nitride film 4 was formed thereon by glow discharge using S I H4, NH3, and N2 as raw material gases. The degree of vacuum was approximately ITorr, and the substrate temperature was 180 to 300°C. After forming the silicon nitride film 4, the entire device is heated by 450'
The temperature was raised to about 50°C, and boron in the a-3t:H film 3 was diffused into the silicon thin film 2. The heat treatment time is 5 to 100 minutes. (Figure 1(b)).

次にチノ化シリコン膜4を160’Cに加熱したリン酸
によってエツチングし、不純物を含むa−Si:Hsを
表面抵抗を測定しながらエツチングして取り除いた。シ
リコン薄膜2を選択エツチングした後、グロー放電によ
って酸化シリコン膜5を形成した。原料ガスはSiHと
NoまたはCO2またはH2Oまたは02の混合ガスを
用いた。従来、シリコン薄膜2の上に酸化シリコン膜5
を形成しただけでは、これらの界面特性は悪(TPT動
作に悪影響を与えていた。本発明では酸化シリコン膜5
の上に第1図fb)と同様の工程でチッ化シリコン膜6
を形成し、素子全体を450°C程度に加熱し酸化シリ
コン膜5の酸素をシリコン薄膜2中に浅く拡散させる。
Next, the silicon tinide film 4 was etched with phosphoric acid heated to 160'C, and a-Si:Hs containing impurities was removed by etching while measuring the surface resistance. After selectively etching the silicon thin film 2, a silicon oxide film 5 was formed by glow discharge. A mixed gas of SiH and No, CO2, H2O, or 02 was used as the raw material gas. Conventionally, a silicon oxide film 5 is formed on a silicon thin film 2.
If only the silicon oxide film 5 was formed, these interface properties would be poor (adversely affecting the TPT operation. In the present invention, the silicon oxide film 5
A silicon nitride film 6 is formed on top of the silicon nitride film 6 in the same process as in FIG.
The entire device is heated to about 450° C. to shallowly diffuse oxygen in the silicon oxide film 5 into the silicon thin film 2.

チッ化シリコン膜6を基板1等との熱膨張係数の差によ
るストレスによって酸素の拡散が促進された。(第1図
(C))再びリン酸でチッ化シリコン膜8をエツチング
し、コンタクトホール20をあける。酸化シリコン膜5
をフッ化アンモンとフッ駿の混合液を用いてエツチング
した。この上に、グロー放電によってS 1 %とPH
3またはA s H3を混合させたガスを用いてa−S
i:H膜7を形成する。n型不純物をa−3i:H膜7
にドープするのはオーミックコンタクトをとりやすくす
るだめである。チン化シリコン膜8を再び形成し、約4
50°Cで熱処理した。(第1図(d)) チン化シリコン膜8、a−8t:H膜7をエツチングす
ると前工程で拡散したリンによってコンタクトホール2
0の下に拡散層9が生じる。金属蒸着膜配線1oを形成
してTPTは完成する。配線10の金属には、Al、T
i、Cr、Ni、Ta、W、Cr等を用いた。
The stress caused by the difference in thermal expansion coefficient between the silicon nitride film 6 and the substrate 1 promoted the diffusion of oxygen. (FIG. 1(C)) The silicon nitride film 8 is etched again with phosphoric acid to form a contact hole 20. Silicon oxide film 5
was etched using a mixture of ammonium fluoride and fluoride. On top of this, S 1% and PH
a-S using a gas mixed with 3 or A s H3
i: H film 7 is formed. n-type impurity a-3i:H film 7
The purpose of doping is to make it easier to establish ohmic contact. The silicon nitride film 8 is formed again, and the thickness of about 4
Heat treated at 50°C. (FIG. 1(d)) When the silicon nitride film 8, a-8t:H film 7 is etched, the contact hole 2 is formed by phosphorus diffused in the previous process.
A diffusion layer 9 is formed under 0. The TPT is completed by forming metal vapor deposition film wiring 1o. The metal of the wiring 10 includes Al, T
i, Cr, Ni, Ta, W, Cr, etc. were used.

実施例 2 前述した実施例1では、ストレスを与える材料としてチ
ン化シリコン膜を用いたが、炭化シリコン膜を用いても
良く、この場合原料ガスとしてばSiHにCHまだはC
2H4,C2H2等の炭化物の混合ガスを用いた。
Example 2 In the above-mentioned Example 1, a silicon nitride film was used as the material to apply stress, but a silicon carbide film may also be used.
A mixed gas of carbides such as 2H4 and C2H2 was used.

実施例 3 ’l’ F Tのゲート酸化膜として酸化シリコン膜を
用いだが、S I H4に炭化物の気体を混合させて作
成した炭化シリコン膜を用いてもTPTは作成できた。
Example 3 Although a silicon oxide film was used as the gate oxide film of the 'l' F T, a TPT could also be created using a silicon carbide film created by mixing carbide gas with S I H4.

実施例 4 TPTのゲート絶縁膜にS IH4とN20まだはN2
の混合ガスによるチン化シリコン膜を用いてもTPTは
作成できた。
Example 4 SIH4 and N20 are added to the TPT gate insulating film.
TPT could also be created using a silicon oxide film using a mixed gas of .

実施例5 コンタクトホール下のオーミックコンタクト用不純物と
してn型不純物の代わりにB2H6,BF3等のドーピ
ングによるp型不純物を用いpチャンネルとしてもTP
Tは作成できた。
Example 5 A p-type impurity doped with B2H6, BF3, etc. is used instead of an n-type impurity as an impurity for ohmic contact under the contact hole, and a TP is also used as a p-channel.
I was able to create T.

実施例6 不純物の拡散を促進するために、チン化シリコン膜、炭
化シリコン膜、酸化シリコン膜と基板との熱膨張係数の
差によるストレスを用いたが、機械的な圧力を加えるこ
とによっても不純物の拡散を促進できた。機械的な圧力
としては、例えば第2図に示すような装置によって本発
明を実施した。
Example 6 In order to promote the diffusion of impurities, stress due to the difference in thermal expansion coefficient between the silicon nitride film, silicon carbide film, silicon oxide film and the substrate was used, but impurities could also be diffused by applying mechanical pressure. was able to promote the spread of As for mechanical pressure, the present invention was carried out using, for example, a device as shown in FIG.

すなわち図3に示した製造途中の半導体素子30を重ね
合わせ、ショックを緩らげるために、重ねた半導体素子
30の上下に石墨31を敷く。これらを基板台32の上
に乗せて天板33を図のように上に置く。半導体素子3
0に圧力を加えるため軸34におもり35を乗せ、ネジ
36で天板33に固定する。石英管37で全体をおおい
、フタ38をして電気炉(図示せず)の中へ導入する。
That is, the half-manufactured semiconductor elements 30 shown in FIG. 3 are stacked one on top of the other, and graphite 31 is placed above and below the stacked semiconductor elements 30 to reduce shock. Place these on the substrate stand 32 and place the top plate 33 on top as shown in the figure. Semiconductor element 3
A weight 35 is placed on the shaft 34 in order to apply pressure to the shaft 34, and it is fixed to the top plate 33 with a screw 36. The entire body is covered with a quartz tube 37, a lid 38 is attached, and the tube is introduced into an electric furnace (not shown).

フタ38のパイプ39から不活性ガス例えばN2.H2
゜八r、f(e等を流して熱処理をする。電気炉の温度
は300〜700℃に設定した。拡散したい部分に有効
に圧力を加えるため第3図に示したように、拡散したい
部分を残して不純物を含むa−8i:H膜50をエツチ
ング形成した。こうして形成した基板3oを第2図のよ
うに重ね合わせると、a−3i:H%aOの部分のみに
上の基板1からの圧力が加わることになる。
An inert gas such as N2 is supplied from the pipe 39 of the lid 38. H2
Heat treatment is carried out by flowing ゜8r, f(e, etc.).The temperature of the electric furnace is set at 300 to 700℃.In order to effectively apply pressure to the area to be diffused, as shown in Figure 3, the area to be diffused is heated. An a-8i:H film 50 containing impurities was formed by etching, leaving the a-3i:H%aO portion.When the substrates 3o thus formed were stacked as shown in FIG. pressure will be added.

圧力の大きさはエツチングして残した面積と荷重によっ
て簡単に計算はできるが、基板等の弾性変形によって大
きな誤差が生じた。荷重をかける治具それぞれで最適値
を求めなければならない。
Although the magnitude of the pressure can be easily calculated using the area left after etching and the load, a large error occurred due to the elastic deformation of the substrate. The optimum value must be found for each jig that applies the load.

本実施例では、5α×10口の石英基板でエツチングで
残す部分を約0.1%とした場合、荷重を5001から
59加えると不純物の拡散が促進された。
In this example, when a 5α×10 quartz substrate was used and the portion left after etching was about 0.1%, impurity diffusion was promoted when a load of 5001 to 59 was applied.

発明の効果 以上述べてきたように、基板上の多結晶シリコンに機械
的な圧力を加えてリン、ホウ素、ヒ素等不純物拡散を加
速させることによって、低温が多結晶シリコンと金属と
のオーミック接触を選択的に行うことができる。さらに
不純物を酸素、炭素。
Effects of the Invention As mentioned above, by applying mechanical pressure to the polycrystalline silicon on the substrate and accelerating the diffusion of impurities such as phosphorus, boron, arsenic, etc., low temperatures can create ohmic contact between the polycrystalline silicon and the metal. It can be done selectively. Further impurities include oxygen and carbon.

チッ素とすることによって、多結晶シリコン表面に絶縁
膜を低温で形成することができ、これらによって、TP
T等、半導体素子を低温で形成することができる。
By using nitrogen, an insulating film can be formed on the polycrystalline silicon surface at a low temperature, and by these, TP
Semiconductor elements such as T can be formed at low temperatures.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例における薄膜トランジスタの
製造方法を示す工程断面図、第2図は本発明の他の実施
例における半導体素子の製造装置の断面図、第3図は基
板に荷重を加える重ね方の一実施例を示した断面図であ
る。 1・・・・・基板、2・・・・・・シリコン薄膜、3.
了、50・・・・・不純物を含むa−8i:H14,6
,8・・・・・・チッ化シリコン膜、9・・・・・・拡
散層、1o・・・・・金属蒸着膜配線、20・・・・・
・コンタクトホール、3o・・・・・・製造途中の半導
体素子、31・・・・・石墨、33・・・・・・天板、
35・・・・・・おもり。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第1図 2      q拡散層 第2図
FIG. 1 is a process cross-sectional view showing a method for manufacturing a thin film transistor according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a semiconductor device manufacturing apparatus according to another embodiment of the present invention, and FIG. FIG. 3 is a cross-sectional view showing an example of how to add layers. 1...Substrate, 2...Silicon thin film, 3.
Completed, 50... a-8i containing impurities: H14,6
, 8... Silicon nitride film, 9... Diffusion layer, 1o... Metal vapor deposition film wiring, 20...
・Contact hole, 3o... Semiconductor element in the process of being manufactured, 31... Graphite, 33... Top plate,
35... Weight. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 1 Figure 2 q Diffusion layer Figure 2

Claims (3)

【特許請求の範囲】[Claims] (1)基板上に低圧気相成長法で多結晶シリコンまたは
非晶質シリコンによるシリコン薄膜を形成し、グロー放
電法で不純物を含む水素化非晶質シリコンを形成し、さ
らにグロー放電法でチッ化シリコン炭化シリコンまたは
酸化シリコンを形成し、上記シリコン薄膜に機械的な圧
力を加えながら加熱することによって上記水素化非晶質
シリコン中に存在する水素を含む不純物を上記シリコン
薄膜に拡散させることを特徴とする半導体素子の製造方
法。
(1) A silicon thin film made of polycrystalline silicon or amorphous silicon is formed on a substrate using a low-pressure vapor phase epitaxy method, hydrogenated amorphous silicon containing impurities is formed using a glow discharge method, and then a silicon film is formed using a glow discharge method. silicon oxide silicon carbide or silicon oxide, and by heating the silicon thin film while applying mechanical pressure, hydrogen-containing impurities present in the hydrogenated amorphous silicon are diffused into the silicon thin film. Features: A method for manufacturing semiconductor devices.
(2)グロー放電法で水素化非晶質シリコンを形成する
際、B_2H_6、BF_3、PH_3、AsH_3、
O_2、N_2O、CO_2、H_2O、CH_4、C
_2H_4、C_2H_2、NH_3、N_2の少なく
も1種類を不純物源として用いることを特徴とする特許
請求の範囲第1項記載の半導体素子の製造方法。
(2) When forming hydrogenated amorphous silicon by glow discharge method, B_2H_6, BF_3, PH_3, AsH_3,
O_2, N_2O, CO_2, H_2O, CH_4, C
2. The method of manufacturing a semiconductor device according to claim 1, wherein at least one of _2H_4, C_2H_2, NH_3, and N_2 is used as an impurity source.
(3)不純物を含む水素化非晶質シリコンを形成した後
、上記不純物を拡散させたい部分のみ選択的にエッチン
グすることを特徴とする特許請求の範囲第1項記載の半
導体素子の製造方法。
(3) The method for manufacturing a semiconductor device according to claim 1, characterized in that after forming hydrogenated amorphous silicon containing impurities, selectively etches only the portion where the impurities are desired to be diffused.
JP5406386A 1986-03-12 1986-03-12 Manufacture of semiconductor element Pending JPS62210618A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5406386A JPS62210618A (en) 1986-03-12 1986-03-12 Manufacture of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5406386A JPS62210618A (en) 1986-03-12 1986-03-12 Manufacture of semiconductor element

Publications (1)

Publication Number Publication Date
JPS62210618A true JPS62210618A (en) 1987-09-16

Family

ID=12960156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5406386A Pending JPS62210618A (en) 1986-03-12 1986-03-12 Manufacture of semiconductor element

Country Status (1)

Country Link
JP (1) JPS62210618A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01183111A (en) * 1988-01-18 1989-07-20 Seiko Epson Corp Manufacture of polycrystalline silicon thin film
US8236709B2 (en) 2009-07-29 2012-08-07 International Business Machines Corporation Method of fabricating a device using low temperature anneal processes, a device and design structure
US8343825B2 (en) 2011-01-19 2013-01-01 International Business Machines Corporation Reducing dislocation formation in semiconductor devices through targeted carbon implantation
JP2016174097A (en) * 2015-03-17 2016-09-29 株式会社東芝 Method for manufacturing semiconductor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01183111A (en) * 1988-01-18 1989-07-20 Seiko Epson Corp Manufacture of polycrystalline silicon thin film
US8236709B2 (en) 2009-07-29 2012-08-07 International Business Machines Corporation Method of fabricating a device using low temperature anneal processes, a device and design structure
US8490029B2 (en) 2009-07-29 2013-07-16 International Business Machines Corporation Method of fabricating a device using low temperature anneal processes, a device and design structure
US8343825B2 (en) 2011-01-19 2013-01-01 International Business Machines Corporation Reducing dislocation formation in semiconductor devices through targeted carbon implantation
JP2016174097A (en) * 2015-03-17 2016-09-29 株式会社東芝 Method for manufacturing semiconductor

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