JPS62206875A - Manufacture of semiconductor memory element - Google Patents

Abstract

PURPOSE:To eliminate the need for an etchback process, and to simplify a manufacturing process largely by depositing polycrystalline silicon only on a layer consisting of silicon or silicon containing nitrogen formed at the bottom of a groove section. CONSTITUTION:A groove 2 in approximately several mum thickness is shaped to an silicon substrate 1 through reactive ion etching, and an oxide film 3 is formed on the inner wall of the groove 2 and the surface of the substrate 1. A film for selective formation is shaped on the inner wall of the groove 2 and the surface of the substrate. Only the film 5 for selective formation on the bottom of the groove 2 is left, and others are removed. Polycrystalline silicon 6 is deposited selectively only in the groove 2 through a CVD method under the conditions of deposition depositing only on the film 5 for selective formation or a surface denaturation layer. An oxide film 7 is formed, and an electrode 8 is shaped, thus completing a groove capacitance section. Accordingly, polycrystalline silicon is deposited only on the film 5 for selective formation, and is not deposited on the oxide film 3 on the surface of the substrate 1, thus eliminating the need for an etchback process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] Undeveloped IJ1 relates to a method of manufacturing a semiconductor memory element using trench capacitance, and particularly relates to a simple method of forming a trench capacitance.

[Prior art] The density of dynamic RAM (DRAM) and MOS memory continues to increase, from 84kbit to 256kbit.
it.

Furthermore, we are about to enter the era of 1Mbit.

For example, a capacitive memory cell has a capacitive part for storing charge and a MOS for reading out the stored charge.
However, in order to achieve high integration, it is necessary to reduce the capacitance section that closes most of the cell surface. This is because the miniaturization of the MOS transistor section is approaching its limit.

Therefore, various methods have been proposed to reduce the capacitance section.

However, simply reducing the capacitance on a two-dimensional plane will reduce the accumulated load. special use must be made of materials that have
Therefore, a trench capacitive memory cell has been proposed that does not require the use of special materials and can be downsized.

FIG. 2 is a schematic cross-sectional view showing the basic structure of a conventional trench capacitive memory cell.

In the figure, a memory cell is composed of a groove capacitor section for accumulating charges and a MOS transistor section for reading out the accumulated charges. Of these, the groove capacitor portion is formed as follows.

First, a deep groove 2 is formed in a silicon substrate 1 by reactive ion etching or the like, and an oxide film 3 is formed on the inner wall of the groove 2. Subsequently, polycrystalline silicon is deposited to form grooves 2.
The polycrystalline silicon 4 is buried in the trench 2 and planarized by etching back to leave the polycrystalline silicon 4 only in the trench 2. In this way, the substrate 1 and the polycrystalline silicon 4 face each other with the oxide film 3 in between, forming a capacitive part.

[Problems that IJI from E is trying to solve] However,
In the process of etching back polycrystalline silicon deposited on areas other than jM2, it has been difficult to detect the end point, so it has not been possible to simplify or simplify the manufacturing process.

[Means for Solving the Problems] A method for manufacturing a semiconductor memory element according to the present invention is a method for manufacturing a semiconductor memory element using trench capacitance, which comprises: forming a trench in a semiconductor substrate;

forming an acid-monide film on the bottom and side walls of the trench and the surface of the substrate, forming a layer of silicon or silicon containing nitrogen only on the oxide film at the bottom, and forming a layer of silicon or silicon containing nitrogen; It is characterized in that polycrystalline silicon is selectively deposited on only the upper portion to fill the trench portion to form a trench capacitance portion.

[Function] In this way, by depositing polycrystalline silicon only on the silicon or nitrogen-containing silicon layer provided at the bottom of the groove, the conventional etch-back process is no longer necessary, and the manufacturing process can be significantly simplified. It can be simplified to

[Examples] Examples of the present invention will be described in detail below with reference to the drawings.
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FIGS. 1A to 1E are partial manufacturing process diagrams showing an embodiment of the method for manufacturing a semiconductor memory element according to the present invention.

First, as shown in FIG.
Then, an oxide film 3 is formed on the inner wall of I11!2 and the surface of the substrate l.

Next, the inner wall of the groove 2 and the substrate surface are coated with a low pressure chemical vapor deposition method, ECR (Electron cyclotron R).
A selective formation film (silicon nitride film or polycrystalline or amorphous silicon film) is formed by the e5onance method or the CVN method using plasma or optical excitation. Subsequently, by lift-off method or reactive ion etching, only the selective formation film 5 at the bottom of the groove 2 is left and the rest is removed, as shown in FIG. 2C.

Note that instead of the selective formation film 5, a resist may be used as a mask and silicon ions or nitrogen ions may be implanted only onto the oxide film 2 at the bottom of the groove 2 at a low acceleration voltage to form a surface metamorphic layer. , and if we use the focused ion beam method,
A similar surface modification layer can be formed without using a mask.

Next, as will be described later, polycrystalline silicon 8 is selectively deposited only in the groove 2 by a CVD method with deposition conditions such that it is deposited only on the selectively formed phase 11'25 or the surface metamorphic layer (FIG. 1(D)). ). Then, as shown in FIG. 3E, after forming an oxide film 7, an electrode 8 is formed to complete the trench capacitor section.

In this way, polycrystalline silicon is deposited only on the selective formation film 5 and not on the oxide film 3 on the surface of the substrate l, so that the conventional etch pack process is not necessary. In addition, by appropriately selecting the deposition rate, polycrystalline silicon B
It is possible to set the height arbitrarily. A specific example of depositing polycrystalline silicon θ will be described below.

First, as shown in FIG. 1(C), the oxidized nq
Selective formation phase of silicon or silicon nitride on a ■I,!
The substrate 1 on which 5 is formed is placed in a reaction tank, and 800 to 1
Maintain at 000°C. Then, under atmospheric pressure, the raw material gas SiH
2012, 5iC14 or SiH4 with HCI and H2
Polycrystalline silicon 6 is deposited by introducing gas. Si
Typical flow when using H2C:I2 gas (Yo, S
iH2G! 2 is 0.5 u/win, HCl is 13
i/+iin, H2 is 150 fl/mir+
It is. Note that by adding 1 (CI gas), the deposition selectivity between the selective formation film 5 and the oxide film 3 is improved.

Under these conditions, the selective formation phase l125k of silicon or silicon nitride is deposited at a deposition rate of 0.03 to 0.08 g.
Polycrystalline silicon 6 was deposited at a rate of m/win, and was not deposited at all on the oxide film 3 on the substrate surface.

[Effects of the invention] - As explained in detail, the unreleased 1! In the method for manufacturing a semiconductor memory element according to II, polycrystalline silicon is deposited only on the silicon layer or the silicon layer containing nitrogen provided at the bottom of the trench, which makes the conventional etch-back process unstable and makes the manufacturing process difficult. The process can be greatly simplified.

[Brief explanation of drawings]

FIGS. 1(A) to (E) are partial manufacturing process diagrams showing an example of a method for manufacturing a semiconductor memory element using undeveloped IJ. FIG. 2 is a basic diagram of a conventional trench capacitive memory cell. FIG. 3 is a schematic cross-sectional view showing the structure. l pot/raised hand conductor substrate 2-... groove 3... oxide film 5Φ... film for selective formation εψ number φ polycrystalline silicon

Claims (5)

[Claims] (1) In a method of manufacturing a semiconductor memory element using trench capacitance, a trench is formed in a semiconductor substrate, an oxide film is formed on the bottom and side walls of the trench, and the surface of the substrate, and only on the oxide film at the bottom. A layer of silicon or silicon containing nitrogen is formed on the substrate, and polycrystalline silicon is selectively grown only on the silicon or silicon layer containing nitrogen to fill the trench and form a trench capacitor. A method for manufacturing a semiconductor memory element. (2) The method for manufacturing a semiconductor memory element according to claim 1, wherein the silicon or nitrogen-containing silicon layer is a polycrystalline or amorphous silicon layer. (3) Claim 1, characterized in that the layer of silicon or silicon containing nitrogen is a silicon nitride layer.
A method for manufacturing a semiconductor memory element as described in 1. (4) The semiconductor memory according to claim 1, wherein the layer of silicon or silicon containing nitrogen is a surface metamorphic layer formed by implanting silicon ions into the surface of the bottom oxide film. Method of manufacturing elements. (5) The layer of silicon or silicon containing nitrogen is a surface metamorphic layer formed by injecting nitrogen ions into the oxidized and de-oxidized surface of the bottom.
A method for manufacturing a semiconductor memory element as described in 1.