FR2595507A1 - METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY ELEMENT - Google Patents

Abstract

THE INVENTION RELATES TO A PROCESS FOR MANUFACTURING A SEMICONDUCTOR MEMORY ELEMENT. IT CONSISTS OF FORMING A TRENCH IN A SEMICONDUCTOR SUBSTRATE, FORMING A FILM OF 3 OXIDE IN THE BOTTOM AND ON A SIDE WALL OF THE TRENCH, AS WELL AS ON A SURFACE OF THE SUBSTRATE, FORMING A FILM WITH SELECTIVE DEPOSITION 5 ONLY ON THE OXIDE FILM IN THE BOTTOM OF THE SLICE, THIS FILM DEPOSITS SELECTIVELY CONSISTING OF SILICON CONTAINING OR NOT CONTAINING NITROGEN, AND TO GROW POLYCRYSTALLINE 6 SILICON ONLY ON THE SELECTIVE DEPOSITION FILM IN ORDER TO FORM A CONDENSER IN SLICE. FIELD OF APPLICATION: MANUFACTURING OF DYNAMIC RAMS, ETC.

Description

The invention relates to a method of manufacturing a memory element to

semiconductor using a

  capacitor in "trench" or "furrow", and more particularly

  a process for easily forming a "trench" capacitor. The density of Dynamic Random Access Memory (DRAM) and Metal-oxide Semiconductor (MOS) memories has increased over the years, and 64 to 256 kbits of memory are being

memories of 1 Mbit or 1 Gbit.

  A conventional capacitive memory cell consists of a capacitor for storing a signal load and a MOS transistor for extracting the signal load for reading. To obtain a higher implantation density, the capacitor occupying most of the surface of the cell must be designed to be compact, because the microgravure of the

  MOS transistor has limitations.

  Various techniques have been proposed to reduce the capacitor size in the memory cell. If the capacitor size is simply reduced in a two-dimensional plane, the amount of signal charge is reduced. To compensate for this, the thickness of the insulating layer placed between the

  electrodes or a material having a con-

  dielectric aunt higher than that of SiO2. A trench capacitor type memory cell is proposed to reduce the capacitor plane extent

  without resorting to the special material indicated above.

  Figure 1 of the accompanying drawing and described below is a schematic cross section showing the structure

  fundamental of a condenser-type memory cell

in trench.

  Referring to FIG. 1, the memory cell comprises a trench or trench capacitor for storing a signal charge, and a MOS transistor for extracting the signal charge from the trench capacitor for reading. The capacitor is formed as follows: A trench or deep groove 2 is formed in a silicon substrate 1 by reactive ion etching or the like. An oxide film 3 is formed on the surface

  of the inner wall of trench 2. Polysilicon

  The crystalline film is deposited so as to cover the entire surface including trench 2. The polycrystalline silicon film is etched back until the surface of the substrate 1 is exposed. In this state, only polycrystalline silicon 4 remains in trench 2. Substrate 1 is opposite polycrystalline silicon 4 through oxide film 3 so as to constitute

a trench capacitor.

  It is difficult to detect a final time of attack

  only in the back-etching or back-etching process of the polycrystalline silicon deposited on the surface of the substrate, excluding trench 2. Therefore, the process

  manufacturing can not be simplified or facilitated.

  The object of the invention is to solve the conventional problems described above, and also to propose a method for manufacturing a semiconductor memory element comprising the steps of:

  to form a trench in a semi-substrate

  driver; forming an oxide film in the bottom and on a side wall of the trench and on a surface of the substrate;

  to form a silicon film or a silicon film

  Cium containing nitrogen only on the oxide film at the bottom of the trench; and

  to selectively grow polysilicon

  only on the silicon film or on the silicon-containing silicon film, so as to form

a trench capacitor.

  The invention will be described in more detail with reference to the accompanying drawings by way of non-limiting example and in which: Figure 1 is a schematic sectional view showing the basic structure of a conventional trench capacitor type memory cell; and FIGS. 2A to 2E are schematic sections for explaining the manufacturing steps of a

  semiconductor memory cell according to the invention.

  FIGS. 2A to 2E are schematic sections for explaining the steps of manufacturing an element

  semiconductor memory device according to the invention.

  As shown in FIGS. 2A and 2B, a trench 2 of a depth of several micrometers is formed in a silicon substrate 1 by reactive ion etching, and an oxide film 3, consisting of SiO 2 or the like, is formed on the surface of the inner wall of the trench

2 and on the surface of the substrate 1.

  Then, a selectively deposited film (for example

  a silicon nitride film, a poly silicon film,

  crystalline lens or an amorphous silicon film) is formed on the surface of the oxide film 3 which corresponds to a part of the surface of the inner wall of the trench 2 and to the part of the surface of the substrate. The formation of the selectively deposited film is carried out by epitaxial growth under low pressure, cyclotron resonance of electrons

  or chemical vapor deposition under plasma or by

  deposition. Selectively deposited film is attacked selectively

  by a detachment, reactive ion etching or the like process so that the film 5 remains only in

  the bottom of the trench 2 as shown in Figure 2C.

  The selectively deposited film can also be formed in the following manner. By using a photoresist pattern as a mask, silicon or nitrogen ions are implanted in the oxide film 3 at the bottom of the trench 2 at a low accelerating voltage in order to denature the surface of the oxide film 3 at the bottom of the trench and thus form a denatured surface layer. In this case, ion beam epitaxy can be used to form a denatured surface layer without the use of a mask to obtain the selective deposition film.

  Polycrystalline silicon 6 is deposited selectively

  in trench 2 by a chemical vapor deposition process, using

  deposition which allows the deposit of polysilicon

  crystalline only in the trench (Figure 2D). Then, as

  shown in FIG. 2E, a film 7 of oxide is formed.

  Finally, an electrode 8 is formed to prepare a conden-

trench.

  The polycrystalline silicon 6 can be deposited only on the selective deposition film 5, but it is not deposited on the oxide film 3 on the surface of the substrate 1. Therefore, unlike the

  conventional method, one can remove the step of retro-attack.

  The thickness of polycrystalline silicon 6 can be determined

  arbitrarily by an appropriate choice of the speed of

  sition. Selective deposition of polycrystalline silicon

  6 only in Trench 2 will be described in detail below.

  below. The substrate 1 carrying the film 5 obtained by deposition of silicon or of a silicon nitride on the oxide film 3 at the bottom of the trench 2 is placed in a reaction chamber.

  predetermined vacuum. Substrate 1 is maintained at a temperature of

  predetermined temperature, for example 900 to 1000 ° C. SiH2Cl2 gas, SiCl4 gas, SiH4 gas or a mixture of these gases is used as a source of gas for the reaction chamber, at a pressure substantially equal to atmospheric pressure so that be selectively

  polycrystalline silicon 6 only on the film 5 to be deposited

  selective In this case, if a carrier gas such as HC1, H2 or a mixture thereof is supplied to the reaction chamber, the deposition efficiency and / or the film quality can be improved. For example, when using

  SiH2C12, HC1 and H2 gas, optimum flow rates

  the evils of these gases are advantageously from 0.1 to 1.0 liter / minute

  1.0 to 2.0 liters / minute and 100 to 200 liters / minute, respectively

  tively. These values vary in association with other deposition conditions. The optimum conditions must be determined for each deposition cycle. An optimal velocity of deposition is determined according to the characteristics desired for an element and it is

  advantageously between 0.03 and 0.08 Lm / minute.

  An example of forming a semiconductor memory element using a trench capacitor will now be described. As shown in Figure 2A, trenches

  2 (only one trench being shown), each of a depth

  5 μm and a width of 3 μm, were formed in a 15 cm silicon wafer (substrate) 15 by reactive ion etching. Using a film-forming apparatus obtained by modifying a commercially available electron cyclotron resonance vapor phase chemical deposition apparatus, an oxide film of SiO 2, 100 nm thick, was formed. thickness, on the surface of the inner wall of each trench 2 and on the surface of the silicon substrate 1 using SiH4 and N20

gaseous (Figure 2B).

  Subsequently, a selective deposition film of Si3N4, 50 nm thick, was selectively formed on the SiO2 oxide film 3 at the bottom.

  from trench 2, using SiH4 and gaseous NH3.

  Substrate 1 was then heated to about 950 C. In this state, the apparatus was supplied with SiH 2 Cl 2, HCl and H 2 gas, respectively constituting source gases and - port eu, at flow rates of 0. , 5 liter / minute, 1.35 liter / minute and 150 liters / minute, under a pressure corresponding to atmospheric pressure, so that polycrystalline silicon 6 is deposited selectively only in trench 2 (Figure 2D). In accordance with training techniques

  known elements in the field of semi-

  conductors, an insulating film 7 of oxide, consisting of SiO 2,

  and an Al electrode 8 were subsequently formed.

  As described in detail above, the method of manufacturing a semiconductor memory element according to this embodiment of the invention can significantly simplify the manufacturing steps and eliminate

  the retro-attack step by depositing polysilicon

  crystalline only on the silicon layer or on the silicon-containing silicon layer, formed in the

bottom of the trench.

  It goes without saying that many modifications can

  can be made to the process described and shown without

depart from the scope of the invention.

Claims (5)

  Method for manufacturing a semiconductor memory element, characterized in that it consists of:   forming a trench (2) in a semi-   driver (1); forming a film (3) of oxide in the bottom and on a side wall of the trench, as well as on a surface of the substrate;   to form a selective deposition film (5)   on the oxide film in the bottom of the trench, the selective deposition film being a member selected from a silicon film and a silicon film containing nitrogen; and   to selectively grow poly silicon   crystalline (6) only on selective deposition film   to form a trench capacitor.   2. Method according to claim 1, characterized in that the selective deposition film comprises a film   of polycrystalline silicon or an amorphous silicon film.   3. Method according to claim 1, characterized in that the selective deposition film comprises a film of silicon nitride.   4. Method according to claim 1, characterized in that the selective deposition film comprises a denatured surface layer obtained by ion implantation.   silicon in a surface of the bottom oxide film.   5. Method according to claim 1, characterized in that the selective deposition film comprises a denatured surface layer obtained by ion implantation.   nitrogen in a surface of the bottom oxide film.