JPS62206853A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62206853A
JPS62206853A JP4846786A JP4846786A JPS62206853A JP S62206853 A JPS62206853 A JP S62206853A JP 4846786 A JP4846786 A JP 4846786A JP 4846786 A JP4846786 A JP 4846786A JP S62206853 A JPS62206853 A JP S62206853A
Authority
JP
Japan
Prior art keywords
film
tungsten
side wall
silicon
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4846786A
Other languages
Japanese (ja)
Inventor
Kyoichi Suguro
恭一 須黒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP4846786A priority Critical patent/JPS62206853A/en
Publication of JPS62206853A publication Critical patent/JPS62206853A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce contact resistance among a metallic layer in an opening section and upper and lower wiring layers, and to prevent an overetching to the lower-layer wiring layer or a semiconductor substrate when forming a side wall film by reacting the side wall film consisting of silicon and the like shaped to the side wall section of the opening section formed to an insulating film by the fluorine compound of a metal employed for burying the opening section. CONSTITUTION:Arsenic is implanted into a P-type silicon substrate 11, an N<+> diffusion layer wiring 12 is shaped through predetermined heat treatment, and an SiO2 film 14 is applied by using SiH4 and N2O at fixed pressure. An opening section is formed by employing a lithographic technique and a dry type etching technique, and a polycrystalline silicon film 15 is applied onto the whole surface of the substrate by using a decompression chemical vapor-phase deposition method. Polycrystalline silicon 15 is etched in an anisotropic manner through reactive ion etching employing a chlorine group gas such as BBr3-Cl2 to leave a side wall film 15a on the inner side wall of the opening section. Tungsten hexafluoride and argon are flowed at prescribed pressure and substrate temperature, and silicon in the side wall film 15a is replaced with a tungsten film 16. Tungsten hexafluoride is reduced, introducing hydrogen gas, and the tungsten film 16 is further grown.

Description

【発明の詳細な説明】 ゛〔発明の目的〕 (産業上の利用分野) 本発明は、半導体装置の製造方法に係わり搭に配縁の接
続部をタングステン等の金属層で埋込んだ半導体装置の
製造方法に関する。
[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and relates to a semiconductor device in which a metal layer such as tungsten is embedded in a wiring connection portion in a tower. Relating to a manufacturing method.

(従来の技術) 従来、半導体装置において上下層の配ルメをつなげるた
δの接続部としてスルーホールを形成し、このスルーホ
ールをタングステン婚のiJl性材料で埋込む方法が採
用されている。この方法を第4図を参照して説明する。
(Prior Art) Conventionally, in a semiconductor device, a method has been adopted in which a through hole is formed as a connection portion of δ to connect the upper and lower layers, and this through hole is filled with an iJl material such as tungsten. This method will be explained with reference to FIG.

つまり、基板■に形成したt又は?シリコン配線層Oj
上にB i 02 gQ、3を形成し、通常のフォトリ
ソグラフィーと反応性イオンエツチングを用いて開孔部
(ハ)即ち、スルーホールを形成する(第4図(a))
。しかる後、減圧したCVD装置内にて六フフ化タング
ステン(WFa)を用いこれをシリコンygIC1υの
シリコンと反応させてシリコン13QD上にタングステ
ン[41を成長させる(第4図(b))。シリコンが六
フフ化タングステンと反応して前記タングステン膜3祷
が一定膜厚になった後はシリコンとの反応はおこらない
ので六ゲステンR1!(24a)を形成するものである
In other words, the t or ? Silicon wiring layer Oj
B i 02 gQ, 3 is formed on top, and an opening (c), that is, a through hole is formed using ordinary photolithography and reactive ion etching (Fig. 4(a)).
. Thereafter, tungsten hexafluoride (WFa) is reacted with the silicon of silicon ygIC1υ in a reduced pressure CVD apparatus to grow tungsten [41] on the silicon 13QD (FIG. 4(b)). After silicon reacts with tungsten hexafluoride and the tungsten film 3 reaches a certain thickness, no reaction with silicon occurs, so tungsten hexafluoride R1! (24a).

この方法に依るとタングステンm(2)1)はその厚さ
が0.5μm程度までは選択的にシリコン配+%1 を
佼C>υ上に形成可能であるが、それ以上になるとS 
t Oz 14 CJ3上においてタングステンの俵形
酸及びそれに続く成長が起こりやすく1選択性を保持で
きなくなるという問題があった。
According to this method, it is possible to selectively form tungsten m(2)1) on C>υ up to a thickness of about 0.5 μm, but if the thickness exceeds that, S
There was a problem in that on tOz 14 CJ3, tungsten pellet acid and subsequent growth were likely to occur, making it impossible to maintain monoselectivity.

この問題点を克服すべく方法として特開昭58−932
55号公報に開示されているよう化第4図において開孔
部(至)の側壁からタングステンを成長させた開孔部を
埋める方法がある。つまり、g5図を用いて詳しく説明
すると、先ず第5図(a)に示すように基板(イ)にt
又は?シリコン配線層なりを形成してこの上に開孔部(
至)を設けたSin、膜(ハ)を形成し、しかる後シリ
コンg(至)を気相成長法等により被着させる。次に第
、5図(b)に示す如く反応性イオンエツチング等でシ
リコン膜(ハ)をエツチングし、側壁部にのみシリコン
膜(25b)を残す。次に六フッ化タングステンを用い
て減圧下でタングステンrsmを形成し、第5図(e)
の如く開孔部(至)を埋める。この方法によれば選択的
なタングステン層(至)の形成は可能であるが、側壁部
に残ったシリコンM(25C)の幅り分だけ、タングス
テン層(2)とその下層のシリコン配線層Qυとの接触
抵抗が増していた。
In order to overcome this problem, Japanese Patent Application Laid-Open No. 58-932
There is a method of filling the opening in which tungsten is grown from the side wall of the opening in FIG. 4, which is disclosed in Japanese Patent No. 55. In other words, to explain in detail using diagram G5, first, as shown in Figure 5 (a), the t
Or? A silicon wiring layer is formed and an opening (
After that, a silicon film (c) is formed, and then silicon (g) is deposited by vapor phase growth or the like. Next, as shown in FIG. 5(b), the silicon film (c) is etched by reactive ion etching or the like, leaving the silicon film (25b) only on the side walls. Next, tungsten rsm was formed under reduced pressure using tungsten hexafluoride, as shown in Fig. 5(e).
Fill the opening (to) as shown. According to this method, it is possible to selectively form the tungsten layer (2), but the tungsten layer (2) and the underlying silicon wiring layer Qυ The contact resistance was increasing.

更に、シリコン#(25b)を8III壁に残す際、S
iO,gfl’l)上のシリコンJ漠(第5図(aJ(
F)(2sa))応しうる技術が望まれている。
Furthermore, when leaving silicon # (25b) on the 8III wall, S
iO,gfl'l) on silicon J(
F) (2sa)) A technology that can meet these requirements is desired.

又、第5図(diに示す如く、上層の配線に例えばアル
ミ(At)配II@を形成し、熱処理を行なう過程で、
前記側壁部のシリコン膜及び下層のシリコン配線層QB
では、シリコンがアルミニウムト反応してシリコン中に
アルミニウムが入り込み、At−Si層(ハ)となって
、いわゆる“つきぬけ“という障害が起こり得る。この
”つきぬけ”部分では処;W基板の温度により体積変化
が起こり、空洞が発生し電気的に悪影響を及ぼすことl
こなる。又SiO!膜翰の下層がPN接合であった場合
、この接合を破壊することになる。
In addition, as shown in FIG. 5 (di), in the process of forming, for example, an aluminum (At) wiring II@ on the upper layer wiring and performing heat treatment,
The silicon film of the side wall portion and the lower silicon wiring layer QB
In this case, silicon reacts with aluminum and aluminum enters the silicon, forming an At-Si layer (c), which may cause a problem called "penetration". In this "penetration" part, the volume changes due to the temperature of the W substrate, creating a cavity, which has an adverse electrical effect.
This will happen. Also SiO! If the lower layer of the membrane is a PN junction, this junction will be destroyed.

(発明が解決しようとする間地点) 本発明は、上記問題点を考慮してなされたもので、タン
グステン等の金属をフンタクトホールあるいはスルーホ
ール等の開孔部の111壁から成長させ、前記開孔部に
タングステン等の埋め込み金属層を形成する半導体装置
の製造方法において、この金属層とこの金属層を介して
接続されている上下配線層あるいは半導体基板との接触
抵抗を低減し、かつシリコン等の半導体膜をエツチング
で側壁部にのみ残す際なされる下層配線あるいは半導体
基板へのオーバーエツチングを防止することを目的とす
る。
(Intermediate Points to be Solved by the Invention) The present invention has been made in consideration of the above-mentioned problems, and is made by growing metal such as tungsten from the 111 wall of an opening such as a hole or a through hole. In a semiconductor device manufacturing method in which a buried metal layer such as tungsten is formed in an opening, the contact resistance between this metal layer and the upper and lower wiring layers or semiconductor substrate connected through this metal layer is reduced, and silicon The purpose of this invention is to prevent over-etching of the underlying wiring or the semiconductor substrate, which occurs when a semiconductor film such as the like is left only on the side wall portion by etching.

〔発明の構成〕[Structure of the invention]

(問題点を解決するための手段) 上記目的を達成するために本発明は、半導体あるいは金
属表面上にこの面が露出するように開孔部を設けた絶縁
膜を形成し、化学気相堆積法で、前記開孔部及び絶縁層
上にシリコン等の半導体膜を被着した後、反応性イオン
エツチングで前記開孔部側壁部に半導体膜を残して、半
導体側壁膜としその後化学気相堆積法により金属のフッ
化物気体を導入してこのフッ化物気体を前記半導体側壁
膜とすべて反応させ、しかる後、前記開孔部を化学気相
堆積法により金属で完全に埋め込むことを特徴とする半
導体装置の製造方法を提供する。
(Means for Solving the Problems) In order to achieve the above object, the present invention forms an insulating film with openings on the semiconductor or metal surface so that this surface is exposed, and deposits the film by chemical vapor deposition. After a semiconductor film such as silicon is deposited on the opening and the insulating layer by a method, the semiconductor film is left on the sidewall of the opening by reactive ion etching to form a semiconductor sidewall film, and then chemical vapor deposition is performed. A semiconductor characterized in that a metal fluoride gas is introduced by a method, the fluoride gas is reacted with the semiconductor sidewall film, and then the opening is completely filled with metal by a chemical vapor deposition method. A method for manufacturing a device is provided.

(作用) 本発明方法によれば、Sin、等の絶縁膜に設けられた
開孔部の側壁部に形成されるシリコン等の側壁膜を前記
開孔部を埋めようとする金属のフッ素化合物で反応させ
ることにより側壁膜を前記金トの低い金属膜を設けるこ
とにより、側壁膜を形成する際の下層配線層あるいは半
導体基板へのオーバーエツチングを防止することができ
る。
(Function) According to the method of the present invention, a sidewall film of silicon or the like formed on the sidewall of an opening provided in an insulating film such as Sin is coated with a metal fluorine compound to fill the opening. By forming the sidewall film with a metal film having a low metal thickness through reaction, it is possible to prevent over-etching of the lower wiring layer or the semiconductor substrate when forming the sidewall film.

(実施例) 本発明による製造方法の一実施例を第1図を用いて説明
する。まず第1図(alの如く、5ΩαのPucioo
)シリコン基板u11にヒX(As)を30KeVで注
入量3xlOclP!  注入し、900℃で一′1; 40分の熱処理を行ないN拡散層(配線)085を形0
.4μmの開口部をリソグラフィー技術と乾式エツチン
グ技術を用いて形成した後、全面に0.1μmの多結晶
シリコン膜(19を減圧化学気相堆積法を用いて、約6
00℃の基板に被着する。しかる後、BBr、−C4等
の塩素系ガスを用いた反応性イオンエツチングで異方的
に多結晶シリコン(151ヲエツチングして、第1図(
b)の如く開孔部内側壁に多結晶シリコンの側壁膜(X
5a)を残す。続いて、圧力0.2 Torr、基板温
度400℃でタングステンのゲステンと反応すると約5
0OAのタングステン膜α0が形成される(第1図(C
))。続いて、水素(H3)ガスを導入しながらこの水
素で六フフ化タングステンを還元して、タングステン膜
αeを更に成長させる。第1図(d)は、水素1t/m
in 、六フッ化タングステン10cc/min 、圧
力0.3’f’orr、基板温度400℃で約20分タ
ングステンを化学気相堆積法で成長させて埋込タングス
テン顛を形成した時の断面形状を示している。又、本方
法により形成したタングステン埋込みを用いて上層にア
ルミニウム配線を形成し、コンタクト特性を評価した結
果、アルミニウム配m/m込タングステンの接触抵抗は
3 X 10−’Ω−2埋込タングステン/ N+拡散
層(As表面濃度2X10cm)の接触抵抗は3〜5X
10 Q−と良好なオーミックコンタクト特性を示し、
ホウ素を2X10 aRで打込んだ〆拡散層の場合も埋
込タングステン配線層散層の接触抵抗は5〜10×10
0−と良好であった。この接触抵抗値は、例えば、第4
図の従来例の場合と比べ1150〜1/100の値であ
る。
(Example) An example of the manufacturing method according to the present invention will be described with reference to FIG. First of all, Fig. 1 (as shown in al, Pucioo of 5Ωα
) Inject HX (As) into the silicon substrate u11 at 30KeV at a dose of 3xlOclP! After implantation, heat treatment was performed at 900°C for 40 minutes to form the N diffusion layer (wiring) 085.
.. After forming a 4 μm opening using lithography and dry etching techniques, a 0.1 μm polycrystalline silicon film (19) was deposited on the entire surface using a low pressure chemical vapor deposition method.
Deposit on a substrate at 00°C. After that, polycrystalline silicon (151) was anisotropically etched by reactive ion etching using a chlorine-based gas such as BBr or -C4, and the polycrystalline silicon (151) was etched as shown in FIG.
As shown in b), a polycrystalline silicon sidewall film (X
5a) remains. Next, when tungsten reacts with Gesten at a pressure of 0.2 Torr and a substrate temperature of 400°C, approximately 5
A tungsten film α0 of 0OA is formed (Fig. 1(C)
)). Subsequently, while introducing hydrogen (H3) gas, the tungsten hexafluoride is reduced with this hydrogen to further grow the tungsten film αe. Figure 1(d) shows hydrogen 1t/m
The cross-sectional shape of an embedded tungsten film formed by growing tungsten by chemical vapor deposition for about 20 minutes at a rate of 10 cc/min of tungsten hexafluoride, a pressure of 0.3'f'orr, and a substrate temperature of 400°C is shown below. It shows. In addition, as a result of forming an aluminum wiring in the upper layer using the tungsten embedded formed by this method and evaluating the contact characteristics, the contact resistance of the aluminum arrangement/m embedded tungsten was 3 × 10-'Ω-2 embedded tungsten/ The contact resistance of the N+ diffusion layer (As surface concentration 2X10cm) is 3~5X
10 Q-, showing good ohmic contact characteristics,
Even in the case of a diffused layer implanted with boron at 2×10 aR, the contact resistance of the buried tungsten wiring layer is 5 to 10×10
The score was 0-, which was good. This contact resistance value is, for example, the fourth
The value is 1150 to 1/100 compared to the conventional example shown in the figure.

次に本発明の他の実施例を第2図を用いて説明する。第
1図と共通な部分は、同一符号で示している。第2図(
a)は第1図(a)で拡散)fJ UJを形成した後、
六フッ化タングステン(WFa)とアルゴン″ゲステン
膜Qeを形成した後(第2図(b) ) 、第2図(C
)に示す如く、埋込みタングステン(lηが形成される
。先の実施例と同様にこの時のコンタクト特性を評価し
た結果、埋込タングステン/タングステン配線層の接触
抵抗は2XlOΩ−,タングステン配線M/N+拡散層
の接触抵抗は5 X 10−’Ωdとやはり良好なオー
ミックコンタクト特性を示した。
Next, another embodiment of the present invention will be described using FIG. 2. Components common to those in FIG. 1 are designated by the same reference numerals. Figure 2 (
a) After forming the diffusion) fJ UJ in Figure 1(a),
After forming the tungsten hexafluoride (WFa) and argon film Qe (Fig. 2(b)),
), buried tungsten (lη) is formed.As a result of evaluating the contact characteristics at this time in the same way as in the previous example, the contact resistance of the buried tungsten/tungsten wiring layer is 2XlOΩ-, and the tungsten wiring M/N+ The contact resistance of the diffusion layer was 5 x 10-'Ωd, which again showed good ohmic contact characteristics.

更に、@2図(a)においてS i 01 H13′(
14下層のオーバーエツチング並びにつきぬけ現象は全
く見られなかった。又、第3図の如く、第2図(C)に
おいてタングステン配線層αJの下がSin!膜081
であっても良い。
Furthermore, in @2 figure (a) S i 01 H13' (
No overetching or penetration phenomenon of the lower layer was observed at all. Also, as shown in FIG. 3, in FIG. 2(C), the area under the tungsten wiring layer αJ is Sin! Membrane 081
It may be.

上記いずれの実施例においても、タングステン腰囲を形
成した後の埋込タングステンu゛0の形成において、°
タングステンの油状速度は表面反応通直で律速させるこ
とにより、更に均一で全洞のない埋込タングステンαη
の形成が可能であり、より信頼性を高めることができる
In any of the above embodiments, in the formation of the embedded tungsten u゛0 after forming the tungsten waist circumference, °
By controlling the speed of tungsten oil through the surface reaction, the embedded tungsten αη is more uniform and has no cavities.
can be formed, and reliability can be further improved.

本発明は上記実施例に限定されるものではなく、例えば
金属表面を構成する金属、即ち配線層03はチタン、ジ
ルコニウム、ハフニウム、ニオブ、タンタル、クロム、
モリブデン、タングステン及びこれらの硅化物又は窒化
物あるいはニッケル、パラジウム、プラチナ及びこれら
の硅化物あるいはアルミニウム、銅を主成分とする金属
のいずれかでもよく、フッ化物を構成する金属はモリブ
デンでありても良い。
The present invention is not limited to the above embodiments, and for example, the metal constituting the metal surface, that is, the wiring layer 03, may be made of titanium, zirconium, hafnium, niobium, tantalum, chromium, etc.
It may be molybdenum, tungsten, their silicides or nitrides, or nickel, palladium, platinum, their silicides, or metals whose main components are aluminum or copper; the metal constituting the fluoride may be molybdenum. good.

〔発明の効果〕〔Effect of the invention〕

以上述べてきたように本発明によれば、0.5μm以上
のコンタクトホール又はスルーホール等の開孔部をタン
グステン等の金属層で完全に埋め込むことができるので
、金JA層と上下配線層との間で良好なオーミックコン
タクト特性が得られる。又、第1の金v4層を設けるこ
とにより、下1mへのオーバーエツチングの影響を防止
する°ことができる。
As described above, according to the present invention, openings such as contact holes or through holes of 0.5 μm or more can be completely filled with a metal layer such as tungsten. Good ohmic contact characteristics can be obtained between the two. Furthermore, by providing the first gold layer V4, it is possible to prevent the influence of over-etching to the bottom 1 m.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例による半導体装置の製造工程
を示す断面図、第2図は、本発明の他の実施例を示す工
程断面図、第3図は本発明のさらに別の実施例を示す断
面図、第4図乃至第5図は従来の製造方法を説明するた
めの断面図である。 11・・・シリコン基板、12・・・1拡散層、13・
・・タングステン膜、14・=SiO,II、15 、
158・・・シリコン膜、16・・・タングステン膜、
17・・・埋込みタングステン、18・・・8i0!I
I。 出願人 工業技術院長 等々力 達 u                 で−ニー   
                         
 −一f5DL 第2図 第3図 第4図
FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view showing a process of manufacturing a semiconductor device according to another embodiment of the invention, and FIG. FIGS. 4 and 5 are cross-sectional views for explaining a conventional manufacturing method. 11...Silicon substrate, 12...1 diffusion layer, 13.
...Tungsten film, 14.=SiO, II, 15,
158...Silicon film, 16...Tungsten film,
17...Embedded tungsten, 18...8i0! I
I. Applicant: Director of the Agency of Industrial Science and Technology Tatsu Todoroki

-1f5DL Figure 2 Figure 3 Figure 4

Claims (5)

【特許請求の範囲】[Claims] (1)半導体あるいは金属表面上にこの面が露出するよ
うに開孔部を設けた絶縁膜を形成し、化学気相堆積法で
前記開孔部及び絶縁膜上に半導体膜を被着した後、反応
性イオンエッチングで前記開孔部側壁部に半導体膜を残
して半導体側壁膜とし、その後化学気相堆積法により金
属のフッ化物気体を導入しこのフッ化物気体を前記半導
体側壁膜とすべて反応させしかる後、前記開孔部を化学
気相堆積法により金属で完全に埋め込むことを特徴とす
る半導体装置の製造方法。
(1) After forming an insulating film with an opening on the semiconductor or metal surface so that this surface is exposed, and depositing a semiconductor film on the opening and the insulating film by chemical vapor deposition. , a semiconductor film is left on the side wall of the opening by reactive ion etching to form a semiconductor side wall film, and then a metal fluoride gas is introduced by chemical vapor deposition, and this fluoride gas reacts with the semiconductor side wall film. After that, the opening portion is completely filled with metal by a chemical vapor deposition method.
(2)金属表面を構成する金属が、チタン、ジルコニウ
ム、ハフニウム、ニオブ、タンタル、クロム、モリブデ
ン、タングステン、及びこれらの硅化物又は窒化物ある
いはニッケル、パラジウム、プラチナ及びこれらの硅化
物あるいはアルミニウム、銅を主成分とする金属のいず
れかである特許請求の範囲第1項記載の半導体装置の製
造方法。
(2) The metal that constitutes the metal surface is titanium, zirconium, hafnium, niobium, tantalum, chromium, molybdenum, tungsten, and their silicides or nitrides, or nickel, palladium, platinum, and their silicides, or aluminum, copper. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is any metal whose main component is.
(3)フッ化物を構成する金属が、タングステン又はモ
リブデンである特許請求の範囲第1項記載の半導体装置
の製造方法。
(3) The method for manufacturing a semiconductor device according to claim 1, wherein the metal constituting the fluoride is tungsten or molybdenum.
(4)フッ化物を用いた化学気相堆積法による金属の堆
積速度が表面反応速度で律速されることを特徴とする特
許請求の範囲第1項記載の半導体装置の製造方法。
(4) The method of manufacturing a semiconductor device according to claim 1, wherein the metal deposition rate by chemical vapor deposition using fluoride is determined by the surface reaction rate.
(5)半導体膜はシリコン膜である特許請求の範囲第1
項記載の半導体装置の製造方法。
(5) Claim 1 that the semiconductor film is a silicon film
A method for manufacturing a semiconductor device according to section 1.
JP4846786A 1986-03-07 1986-03-07 Manufacture of semiconductor device Pending JPS62206853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4846786A JPS62206853A (en) 1986-03-07 1986-03-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4846786A JPS62206853A (en) 1986-03-07 1986-03-07 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62206853A true JPS62206853A (en) 1987-09-11

Family

ID=12804179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4846786A Pending JPS62206853A (en) 1986-03-07 1986-03-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62206853A (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5842227A (en) * 1981-09-07 1983-03-11 Toshiba Corp Manufacture of semiconductor device
JPS5893255A (en) * 1981-11-30 1983-06-02 Toshiba Corp Manufacture of semiconductor device
JPS6286818A (en) * 1985-10-14 1987-04-21 Fujitsu Ltd Manufacture of semiconductor device
JPS62141739A (en) * 1985-12-16 1987-06-25 Matsushita Electric Ind Co Ltd Manufacture of semiconductor integrated circuit
JPS62179745A (en) * 1986-02-04 1987-08-06 Nec Corp Manufacture of semiconductor device
JPS62204523A (en) * 1986-03-04 1987-09-09 Nec Corp Forming method for contact electrode

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5842227A (en) * 1981-09-07 1983-03-11 Toshiba Corp Manufacture of semiconductor device
JPS5893255A (en) * 1981-11-30 1983-06-02 Toshiba Corp Manufacture of semiconductor device
JPS6286818A (en) * 1985-10-14 1987-04-21 Fujitsu Ltd Manufacture of semiconductor device
JPS62141739A (en) * 1985-12-16 1987-06-25 Matsushita Electric Ind Co Ltd Manufacture of semiconductor integrated circuit
JPS62179745A (en) * 1986-02-04 1987-08-06 Nec Corp Manufacture of semiconductor device
JPS62204523A (en) * 1986-03-04 1987-09-09 Nec Corp Forming method for contact electrode

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