JPS62204642A - Line scanning control system - Google Patents

Abstract

PURPOSE:To attain efficient use of an LCW memory by storing a line control word LCW used in common during each service period of a transmission/ reception channel in the common use LCW memory. CONSTITUTION:The common LCW memories 116-118 accessed by a transmission and reception channel addresses are provided and a line control word used in common is stored in the common use LCW memories 116-118 during the transmission channel service period and the reception channel service period. Thus, the number of line control words stored in the LCW memory device 110 is decreased.

Description

[Detailed Description of the Invention] [Summary] In a line scanning control method of a communication control processing device, a line control word (LCW) that is shared for transmission and reception channels is used.
), and performs transmission and reception line scanning control by referring to the shared LCW memory as well as the respective transmission and reception LCW memories during each service period of the transmission channel and reception channel. This allows the number of words in the LCW to be reduced and the LCW memory to be used efficiently.

[Industrial application field]

The present invention relates to a line scanning control method in a line adapter provided in a communication control processing device, and in particular, to reducing the number of line control words stored in a line control word memory without degrading the line scanning control function. This invention relates to a line scanning control method that allows for efficient use of.

[Conventional technology]

The communication control processing device is interposed between the communication line and the host processor, and has internal channel adapters, line adapters, central processing units, etc., and handles data between the host processor and other computer systems and terminal devices connected to the communication line. Performs necessary control when performing transmission.

At that time, the channel adapter controls data transfer between the host processor and the communication control processing unit, the line adapter controls data transmission and reception between the communication line and the communication control processing unit, and the central processing unit has a control program inside. (NCP
: Network control program
), and controls overall communication control operations performed by the communication control processing device, including control of channel adapters and line adapters.

FIG. 5 is a block diagram showing the basic configuration of the line adapter.

In FIG. 5, 200 is a line adapter, and 300 is a system bus within the communication control processing device.

In the line adapter 200, 210 is a control memory in which control programs and data for controlling the operation of the line adapter 200 are stored.

220 is a line scanning unit, which includes a plurality of line control word memories (LCW memories) 221. -2217, and performs line scanning control and control of disassembly/assembly of transmitted and received characters. L
CW memory 221. -2217 have LCW memories for the transmission channel and for the reception channel, the former stores the line control word (LCW) for the transmission channel, and the latter stores the LCW for the reception channel.

230 is a line connection device interface that performs interface and connection operations with a communication line.

A system bus control unit 240 interfaces between the system bus 300 and the line adapter 200, and controls the transfer of data and control information to and from a central processing unit (not shown).

A processor (MPU) 250 controls the line adapter 22 including control over the line scanning unit 220 and system bus control unit 240 under the control of a control program stored in a control memory.
Controls the entire operation of 0.

[Problem that the invention seeks to solve]

In the line adapter of the conventional communication control processing device, as mentioned above, the LCW for the transmitting channel and the LCW for the receiving channel are stored in separate LCW memories in the line scanning section, and the line scanning control is performed during the transmitting and receiving channel service. was going on.

However, since each LCW memory for transmitting and receiving channels is built on a semiconductor chip, the LCW memory due to its configuration is
Currently, the scale of CW memory is small and is limited to small capacity.

For this reason, when the number of channels is increased, the capacity of each LCW memory decreases, the number of line control words set in the LCW decreases, and the line scanning control function deteriorates; conversely, increasing the number of line control words improves the line scanning function. If you try to do this, there is a problem that you will have to reduce the number of channels.

The present invention enables LC scanning without deteriorating the line scanning control function.
It is an object of the present invention to provide a line scanning control method that reduces the number of LCW words stored in a W memory and allows efficient use of the LCW memory under limited capacity.

[Means for solving problems]

The means taken by the present invention to solve the above-mentioned problems in the conventional line scanning system will be explained with reference to FIG.

FIG. 1 is a block diagram showing the basic configuration of the present invention.

In FIG. 1, 100 is a line scanning section of a line adapter, which corresponds to the line scanning section 220 in FIG. 5 and performs line scanning control.

Reference numeral 110 denotes a line control word memory means (LCW memory means) in which the LCW for the transmission and reception channels is stored, in which the LCW used in common as the LCW for the transmission and reception channels is stored together with the LCW for the transmission or reception channels. A shared line control word memory (shared LCW) that is accessible during both channel and receive channel service periods.
memory).

120 is a scanning address control means which controls the transmission channel address of one line during a scan cycle for the line;
Generate the receive channel address and the receive channel address of the next line to be scanned.

Reference numeral 130 denotes a line scanning control means, during the transmission channel service period of the scan cycle, the LCW memory means 11 is stored in accordance with the address generated by the scan address control means 120.
The scan address control means 120 performs transmission line scanning control by accessing the transmission channel LCW memory and shared LCW memory within 0, and during the reception channel service period.
The receiving channel LCW memory and the shared LCW memory in the LCW memory means 110 are accessed by the address generated by the receiving line scanning control.

[For production]

The line scanning control means 130 performs transmit channel service and receive channel service during the scan cycle of one line.

During the transmission service period, transmission line scanning control is performed using the address generated by the scanning address control means 120 while referring to the transmission channel LCW and shared LCW memory in the LCW scanning 11O.

During the reception service period, the reception line scan control is performed by referring to the reception channel LCW memory and the shared LCW memory in the LCW scan 110 using the address generated by the scan address control means 120.

As described above, a shared LCW memory that can be accessed by a transmitting channel address and a receiving channel address is provided, and LCWs that are commonly used during the transmitting channel service period and the receiving service period are stored in this shared LCW memory.
, the number of LCW words stored in either the transmitting or receiving LCW memory can be reduced by the number of LCWs stored in the shared LCW memory. Therefore,
The number of LCW words stored in the LCW memory device 110 can be reduced and the LCW memory can be used efficiently.

〔Example〕

Embodiments of the present invention will be described with reference to FIGS. 2 to 4.

FIG. 2 shows a block diagram of the configuration of an embodiment of the present invention, and FIG. 3 shows a shared LCW used in the embodiment.
FIG. 4 is an explanatory diagram of the LCW memory including the following, and is a time chart during full-duplex scan operation of the same embodiment.

(A) Configuration of Embodiment In FIG. 2, the line scanning unit 100, line control word memory means (LCW memory means) 110, scan address control means 120, and line scanning control means 130 are as explained in FIG. It is.

In the LCW memory means 110, 111 to 115 are line control word memories (LCW memories) in which line control words (LCW) for transmission channels or reception channels are stored.

116 to 118 are shared line control word memories (shared LCW
(memory), the LCW shared by both is stored together with the T and CW for the transmit or receive channel.

Each of the shared LCW memories 116 to 118 is a well-known 2-port random access memory (2-port random access memory) in this embodiment.
AM).

2-bot RAM has two addresses (A system and B system (B,
~B2)), and in the case of address A, reading and writing are possible, but in the case of address B, it is a RAM that can only be read.

The scan address control means 120 generates a transmission channel address n, a reception channel address (n+1), and a reception channel address (n+3) of the line to be scanned next using a scan counter (not shown). These addresses allow the LCW memories 111 to 115 and the shared LCW
A system address (L
CW address A), and B system addresses (LCW addresses 80 to BX) that access shared LCWs 116 to 118.
) is used as In addition, LCW addresses A, B, ~
Since Bt changes during the transmission service period, reception service period, etc., the address value at each operation is, for example, A.
(rt), A (n+1) (these LCWA, B, ~B2 will be explained in detail in the section (B) Operation of the embodiment below).

In the line scanning control means 130, 131 is a data-in register, into which data or LCW from the adapter's processor (MPU) or control memory (none of which are shown) is transferred from the internal bus and set. 132 is a data out register in which data or LCW to be transferred to the MPU or control memory is sent. 133 is a calculation unit that performs calculations based on data or information transferred from the data out register 132, the LCW memory means 110, and an external line connection device interface (not shown), and outputs the results according to the processing content. Data out register 132
, LCW memory means 110, or line connection device interface. 134 is an internal timing control section;
Internal timings (T0 to TII, etc., see FIG. 4(a)) that define the operations performed by each part within the line scanning section 100 are generated. 135 and 136 are receivers and drivers for system bus connections.

Next, a specific example of the shared LCW memory (116 to 118) will be explained with reference to FIG.

FIG. 3(A) shows an example of an LCW memory including a shared LCW in which a shared LCW is stored together with a transmitting LCW, and the synchronization pattern data stored in area 1 is
It is accessed by CW address A and LCW address B0 and is used during both the transmit channel and receive channel service periods.

FIG. 3(B) shows an example of an LCW memory including a shared LCW in which a shared LCW is stored together with a receiving LCW, and data of modem control 1 in area 3 is accessed by LCW address A and LCW address B+. and is utilized during both the transmit and receive channel service periods.

(B) Operation of the Embodiment The operation of the embodiment will be explained with reference to the time chart of FIG. 4, taking the full-duplex scanning method as an example. In FIG. 4(a), T0 to Tl+ indicate internal timing.

In the full-duplex scan method, one line scan cycle (T0 to TII) is a program cycle (T0
-T:l) and scan cycle (T4-T11), and the scan cycle is further divided into a transmit cycle (T4-T7) where transmit channel service is performed and a receive cycle (T8-T11) where receive channel service is performed. (Fig. 4 (a), (b)).

In this scan cycle, the scan counter is initially n, and when n is set to a scan address (not shown), it counts up to (n+2) in the next scan cycle. The scan address register holds this value of n as a scan address during the scan cycle (FIGS. 4(c) and 4(d)).

In addition, the shared LCW is stored in the shared LCW memories 116 (LCW addresses are A and BO) and 117 (LCW addresses are A and Bt) together with the receiving LCW (see FIG. 3 (B)).
), and the shared LCW memory 115 (LCW addresses are A and Bl) stores the shared LCW together with the transmitting LCW (see FIG. 3(A)). The operation in each cycle will be explained separately below.

(B-1) Operation in the program cycle In the program cycle (T0 to T), the line adapter M
The PU accesses the LCW memory in the LCW memory device 110.

The MPtJ and line scanning control means 130 performs a read process of the LCW in the LCW memory area of the desired address (m) in the read cycle R of this program cycle, and reads the line scanning unit in the LCW memory area of the desired address (m) in the write cycle W. The LCW write process for 100 is performed. The LCW address A(m) for accessing the LCW mesori area is supplied by the scan address control unit 120.

(B-2) Operation in Transmission Cycle In the transmission cycle (T4 to T?), transmission channel service is performed. During the transmit cycle, the scan counter is set to (n + 2), and the scan address and register hold scan address n (see Figure 4).
c), (d)). Furthermore, scan address control means 1
20 generates n as LCW address A and n,,B as LCW address Bo.

and (n+1) is generated as B2 (Figure 4 (gl~
(1)).

In the read cycle R during the transmission cycle, the calculation unit 1
33 accesses the desired transmission LCW memory using the LCW address A (n), and accesses the shared LCW memory 11 using the LCW address B+ (n +1).
7 (Figure 4 +2) to (j)).

The shared LCW memory 117 has a configuration as shown in FIG. 3(B), and reads the contents of the modem control 1 and detects changes in the modem status, for example, when the ready-to-send signal C8 sent from the modem changes from off to on. By detecting this, an instruction to start transmission is created. In response to this transmission start instruction, line data out information is transferred to the line connecting device interface at internal timings T6 and T (FIGS. 4(a), (b), and (nl)).

(B-3) Operation in the reception cycle Reception cycle (
T, ~T + + ), receive channel service is performed. During the receive cycle, the scan counter is set to (n+2) and the scan address register holds scan address n (Figure 4 [C), (
d)). Further, the scan address control unit 120 controls the LCW
Generate (n+1) as address A and n as LCW address B0.

(n+1) is generated as B1, and (n+3) is generated as Bz (FIG. 4(a-(1)).

In the read cycle R during the transmission cycle, the calculation unit 1
33 accesses the desired receiving LCW memory using LCW address A(n+1), and accesses the shared LCW memory 116 using LCW address B(1(n) (FIG. 4 fe) to ('')).

The shared LCW memory 116 has a configuration as shown in FIG. 3(A), and a synchronization pattern is stored in area 1.

BSC (Binary 5ynchronous
In the communication) procedure, a reference synchronization pattern is required to monitor the synchronization pattern of received data, but this reference synchronization pattern is
It is obtained by reading the synchronization pattern from the shared LCW memory 116. Note that this synchronization pattern is incorporated into transmission data during transmission channel service.

Further, the calculation unit 133 accesses the shared LCW memory 118 using the LCW address Bz(n+3), and uses the physical address stored in the physical line address area (see FIG. 3(B)), that is, the target of the next line scan. The line address (N+3) is read and set in a line address register (not shown). This line address ('N+3) is transferred to the line connecting device interface at internal timing T1° and Tl+ (Fig. 4 (k1 to (1)
). Note that the line address (N+1) in the current line scan cycle stored in the line address register
) is the internal timing (T,
. , 'r,1').

The line connection device interface uses this line address (N
+3), it starts scanning the next line.

Although the embodiment in the case of the full-duplex scan method has been described above, the present invention is not limited to this embodiment, and can also be used in the case of the half-duplex scan method.

〔Effect of the invention〕

As explained above, according to the present invention, the following effects can be obtained.

(a) By sharing the line control word LCW during each service period of the transmission and reception channels, the number of line control words can be reduced without degrading the line scanning control function.

(b) According to (b) above, if the number of line control words is the same, the capacity of the line control word memory can be decreased; if the capacity of the line control word memory is the same, the number of channels or the number of line control words can be increased. The line control function can be improved by increasing the number of lines.

[Brief explanation of drawings]

Fig. 1...Explanatory diagram of the basic configuration of the present invention, Fig. 2...
FIG. 3 is an explanatory diagram of the configuration of an embodiment of the present invention. FIG. 4 is an explanatory diagram of a line control word memory including a shared line control word used in the embodiment. Time chart during heavy scan operation. Figure 5: An explanatory diagram of the basic configuration of the line adapter. 1 and 2, 100... line scanning section, 110... line control word (L
CW) memory means, 120...scan address control means, 130... line scan control means.

Claims (2)

[Claims] (1) In a line scanning control method of a line adapter installed in a communication control processing device, (a) a line control word that is shared as a line control word for transmitting and receiving channels together with a line control word for a transmitting channel or a receiving channel; line control word memory means for storing transmit and receive channel line control words, comprising at least one shared line control word memory in which are stored and accessible during both the transmit and receive channel service periods;
(110); (b) scan address control means (120) for generating, during a scan cycle for one line, a transmit channel address, a receive channel address for that line, and a receive channel address for the next line to be scanned; c) During the transmission channel service period of the scan cycle, access the transmission channel line word memory and the shared line control word memory in the line control word memory means (110) using the address generated by the scan address control means (120); During the reception channel service period, the scan address control means (120
), a line scanning control means (130) performs receiving line scanning control by accessing a receiving channel line control word memory and a shared line control word memory in the line control word memory means (110) using the generated address. A line scanning control method characterized by: (2) The line scanning control system according to claim 1, wherein the shared line control word memory is comprised of a two-port random access memory.