JPS62203361A - Integrated circuit with built-in chip name display circuit - Google Patents

Abstract

PURPOSE:To facilitate the confirmation of correspondence between IC chips and test patterns thereof by a method wherein two way buffers to output chip name displaying signals from clamp.source circuits as well as a control terminal to control the two way buffers are provided. CONSTITUTION:When chip name display circuit control signals 20 from a chip name display circuit control terminal 11 are at the '0' level, two way buffers 21-24 input the input signals from terminals 11-14 to an inner logic circuit 13 as input signals 31-34. In case of testing ICs, the signals 20 are turned to the level '1' to change-over the signal conductive directions of buffers 21-24 so that the chip name displaying signals 41-44 proper to the ICs outputted from clamp.source circuit 12 may be outputted to two way terminals 11-14 through respective buffers 21-24. Through these procedures, any chip names can be confirmed easily to judge the adequacy and inadequacy of chips for the test pattern thereof.

Description

[Detailed description of the invention] "Industrial application field" The present invention relates to integrated circuits with reduced test errors.

``Prior Art'' Conventionally, the correspondence between product names of integrated circuits and test patterns necessary for circuit testing has been left to management on the medium in which the test patterns are stored.

"Problems to be Solved by the Invention" As mentioned above, in the past, the correspondence between product names of integrated circuits and the test patterns necessary for circuit testing was left to the management of the medium in which the test patterns were stored. As the trend towards small-volume, high-mix integrated circuits increases, the environment is becoming more likely to cause inconsistencies in checking the correspondence between integrated circuit chips and test patterns, and these inconsistencies lead to unnecessary time being wasted in redoing tests and analyzing failures. The disadvantage is that it is likely to require

"Means for Solving the Problem" According to the present invention, there is a clamp source circuit that outputs a chip product name display signal, a bidirectional buffer that can output the chip product name display signal, and a connection to the bidirectional buffer. The integrated circuit is provided with a bidirectional terminal that is configured to control the bidirectional buffer, and a control terminal that receives a signal that controls the bidirectional buffer.
Ru.

When testing this integrated circuit, the bidirectional buffer is controlled by the control signal of the control terminal to output the chip product name display signal to the bidirectional terminal through the bidirectional buffer, and the integrated circuit is tested using this chip product name display signal. By confirming that the test pattern required for the product name corresponds to the product name, inconsistencies between the two can be quickly discovered.

"Example" Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which a chip product name is displayed using 4 bits, and FIG. 2 is a truth table of FIG. 1.

In this invention, a chip product name display circuit is provided on an integrated circuit chip. In the example shown in FIG. 1, the chip product name display circuit includes bidirectional terminals 11112.13.14 and a bidirectional buffer 2 connected to these bidirectional terminals 11.12.13.14.
1.22.23.24, a chip product name display circuit control terminal 11, and a clamp source circuit 12 that outputs the chip product name display.

When the chip name display circuit control signal 20 of the chip name display circuit control terminal 11 is a ttOn signal, the bidirectional buffer 2□
, 22.23.24 is terminal 11+ 12+ IL 1
The input signals from 31.4 are input to the internal logic circuit 13, respectively. ．． 32, 33, and 34, and performs the original function of an integrated circuit.

During a circuit test of the integrated circuit, the chip product name display circuit control signal 20 of the terminal 11 is set to the "11" level, and this tt
1 n level switches the signal conduction direction of the bidirectional buffer 21, 22, 23, 24 through the fan-out gate 14, and outputs the integrated circuit product name display signal 41142.43 from the clamp source circuit 12. 44
are output to the bidirectional terminal 11.12.13.14 through the bidirectional buffers 21.22.23.24, respectively,
This output makes it easy to confirm the chip product name.
Compatibility or non-conformity between the chip and the test pattern can be determined. FIG. 1 shows a 4-bit example of a chip product name display signal unique to an integrated circuit, and designated chip product name display signals 41, 42, 43, and 44 are used in the clamp source circuit 1.
2 to 11111, 110I+, 11Qil
.

Only when this is output as tt 1 n to the bidirectional terminal 11.12.13.14 which is the observation point, is the compatibility between this integrated circuit chip and the test pattern used during circuit testing confirmed.

"Effects of the Invention" As explained above, the present invention provides a circuit that outputs a product name display signal consisting of an arbitrary pit width in order to identify the product name of an integrated circuit chip, and a circuit that outputs the product name display signal for observation. By providing an arbitrary number of bidirectional buffers, bidirectional terminals, and control terminals for controlling the bidirectional buffers, a product name display signal can be output during testing, and integrated circuit chips and test patterns can be easily identified during circuit testing. This has the effect of eliminating wasted time such as redoing the test due to inconsistency between the two, inability to analyze failures, and reconfirming management on the test pattern storage medium.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a main part of an integrated circuit incorporating a chip product name display circuit according to the present invention, and FIG. 2 is a diagram showing a truth table of FIG. 1. 11-1 now: bidirectional terminal, 21-24: bidirectional buffer, 31-34: input signal of internal logic circuit, 41-4
4: Product name display signal, 11: Chip product name display circuit control terminal, 12: Clamp source circuit, 14: Fan-out gate, 20: Chip product name display circuit control signal.

Claims (1)

[Claims] (1) A clamp source circuit that outputs a chip product name display signal, a bidirectional buffer that can output a chip product name display signal of the clamp source circuit, and a bidirectional terminal connected to the bidirectional buffer; and a control terminal into which a signal for controlling the bidirectional buffer is input, and an integrated circuit incorporating a chip product name display circuit.