JPS62202612A - Master slave latch circuit - Google Patents

Abstract

PURPOSE:To prevent racing, to reduce gate number and to attain high density by sharing a latch gate of a master latch for a data gate of a slave latch. CONSTITUTION:Specific gates 12, 17 are shared for the master latch and the slave latch to form a master-slave latch circuit. Through the constitution above, a signal enters a gate 14 of the slave latch through the gate 12 of the master latch and enters the gate 19 of slave latch through the gate 17 similarly, then no racing takes place theoretically. Further, since the gates 12, 17 are shared, one clock driver is enough, the data gate exclusive for the slave latch is not needed and the gate number is reduced remarkably.

Description

[Detailed Description of the Invention] [Summary] A circuit configuration is provided in which a part of the gate of the master latch is shared with the gate of the slave latch. Such a master-slave latch circuit can prevent racing and reduce the number of gates.

[Industrial application field]

The present invention relates to a master-slave latch circuit, and particularly to improvements in its constituent circuits.

As is well known, the master slave latch is an extremely important circuit in the configuration of logic circuits, regulating the temporal order of inputs.
This is a typical so-called sequential circuit.

Therefore, it is desirable that the latch circuit has high reliability and low power consumption.

[Prior art and problems to be solved by the invention] FIGS. 6(a) and 6(b) illustrate two types of conventional launch circuits, and FIG. 6(a) is composed of an OR gate, The data signal (+D) is input to OR gate 1 (data gate), and from clock driver CD to OR gate 1.
70 clock (-CLK), + clock (-CLK) to OR gate 2
+CLK) is input, and the OR gate 2 and dot gate 3 (collector AND gate) are used as flip-flops.

Further, FIG. 4(b) is a launch circuit composed of NOR gates, in which a data signal (+D) is input to NOR gate 4 (data gate) and inverted, and NOR gates 5 and 6 are made into flip-flops.

A master-slave latch circuit can be formed by appropriately combining two of these latch circuits.
This is a master-slave branch circuit formed by combining the same latch circuits shown in a).

In the figure, 1°, 2', 3', and CD' are respectively 1.2.3. This indicates that it is the same gate circuit as the CD. In addition, here is the clock driver CD, CD
' cannot be shared because both have opposite phases, and if they are shared, the skew required for circuit operation cannot be removed.

FIG. 8 shows a time chart of signals of the master-slave branch circuit shown in FIG. 7, in which +D is a data signal, -
CLOCK is the input clock signal, a is the output C line signal from the clock driver CD (-CLK), and b is the output b line signal from the clock driver CD (+CLK).
), c is the output C line signal (+CIJ) from the clock driver CD'.

d is a signal (-CLK) on the output d line from the clock driver CD', e is a signal on the C line of the flip-flop gate of the master section, and f is a signal on the output line from the slave section.

By the way, in such a circuit configuration, each gate has different operating characteristics, so one signal on the C line may arrive earlier than the skewed child signal on the C line. Yes, then racing (malfunction) will occur.

In FIG. 8, solid lines C and f are waveforms during normal operation, and broken lines C and f are waveforms when malfunction occurs.

In normal operation, when the signal falls, the data signal less appears as the output signal e of gate 3, and by the time this output signal e appears, signal C has already risen, so OR gate 1 does not transmit the signal e to its output. In other words, OR gate 1' is in a closed form, so to speak. After that, when signal C falls, OR gate 1
transmits the signal e to its output. That is, or gate 1 is opened. Then, the signal e is output as the signal f from the gate 3'.

In other words, under normal conditions, the master-slave latch outputs to the master latch at the leading edge of the clock, the slave launch is closed during the clock period, and the output appears to the slave latch at the trailing edge of the clock. . However, as shown by the broken line in FIG. 8, if signal C arrives later than signal e, OR gate 1° remains open at the time signal e appears, and OR gate '1° will transmit the signal e to its output side. As a result, the gate 3'' outputs the signal e as the signal f. In other words, a racing operation occurs in which the output is already output to the slave side at the leading edge of the clock.

This is not limited to the master-slave latch circuit shown in FIG. 7, but also applies to master-slave latch circuits in which other types of latch circuits are combined.

The present invention proposes a master slave latch circuit having a circuit configuration that eliminates the possibility of racing.

[Means for solving problems]

This problem is solved by a master-slave branch circuit in which the latch gate of the master launch is shared as the data gate of the slave branch.

[For production]

The present invention forms a master-slave latch circuit in which a master latch and a slave latch share one specific gate.

In this way, racing can be prevented and the number of gates can be reduced.

〔Example〕

Hereinafter, embodiments will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of a first embodiment of a master-slave latch circuit according to the present invention, and this example replaces the conventional latch circuit consisting of a NOR gate shown in FIG.
This is an example of a circuit in which two gates are combined and one gate is shared. In the figure, 11, 12, and 13 are the gates of the master latch (of which 12.13 is a flip-flop configuration), and 12° and 14.15 are the gates of the slave latch (of which 14.15 is a flip-flop configuration). , the gate constructed in the emitter follower output circuit is a gate shared by the master latch and slave latch. That is, the gate 12 is a free-knob flop gate for the master latch, and also serves as a data gate for the slave latch.

Further, FIG. 2 shows a block diagram of a master slave latch circuit according to a second embodiment of the present invention, and this example is different from the conventional latch circuit shown in FIGS. 6(a) and 6(bl). This is an example of a circuit that is combined and shares one gate. 16, 17.18 are master launch gates (of which 17.18 is a flip-flop configuration), 17.1
9.20 is the gate of the slave latch (19.
20 is a flip-flop configuration), and the gate 17 is a gate shared by the master latch and the slave latch.

With this configuration, the signal is sent to gate 1 of the master latch.
2 and enters the gate 14 of the slave latch (first
(in the case shown in the figure), and also passes through the gate 17 and enters the gate 19 of the slave latch (in the case shown in Fig. 2).
Theoretically, racing cannot occur. In addition, since one gate 12, 17 is shared, there is only one clock driver, and there is no data gate dedicated to the slave branch, which greatly reduces the number of gates.

FIG. 3 shows a time chart of the master slave latch circuit shown in FIG. 1, where +D is a data signal.

A is the signal (No. 8 (CLK)) of the output A line from the clock driver CD, B is the signal (+CLK) of the output B line from the clock driver CD, -D is the output card D of the gate 11
Similarly, F is the output (master output) signal of gate 13, Po is the output of gate 12 and gate 14
, and S is the slave output signal.

FIG. 4 shows a specific circuit example of the gate 12 shared by both latch circuits, and the symbols in the figure correspond to those in FIG. 1. In the figure, Ql is the clock signal (+CL
C2 is a transistor that inputs the master output signal, C3 is a transistor that inputs a reference voltage, and C4 and C5 are emitter follower transistors that take out the output.

By the way, in order to prevent the slave latch of such a master slave latch circuit from malfunctioning, C1o
The signal transmission speed of ck −” +CLK −P′ is C
It is necessary that the signal transmission speed is slower than the signal transmission speed of 1ock→+CLK→P, and this can be done by providing a skew in the +CLK signal or by slowing down the fall of P''.To delay the fall of Po, the transfer speed of transistor Q5 It is effective to make the resistance of the emitter follower larger than the resistance of the emitter follower of the transistor Q4, or to attach a capacitor to the output of the transistor Q5.Also, a delay gate may be inserted into P''.

FIG. 5 shows a specific circuit example of the shared gate 17, the adjacent gate 16, and the dot gate 18 in the master-slave branch circuit shown in FIG. The part that connects the collectors of both gates is the gate 1B circuit.

FIG. 9 is a circuit block diagram of a third embodiment of the present invention. In the same figure, 30 is a clock driver, 31, 3
2.33 is the gate that constitutes the master latch, 32.34
．． 35 is a gate constituting a slave branch. In this example, 32 is a common gate.

The embodiment shown in FIG. 9 is a slight modification of the embodiment shown in FIG.
l, CNT2 is added, and the data gate 3 of the master latch is
1 is connected to two input data lines, and furthermore, the inverted output signal Q of each master/slave is also taken out.

FIG. 10 is a circuit block diagram of a fourth embodiment of the present invention, in which 40 is a clock driver;
42.43 are gates forming the master latch, 42,4
4.45 is a gate that constitutes a slave latch, 46.4
7 is a gate added as necessary when increasing input data. In this example, 42 is the common gate.

FIG. 11 is a circuit block diagram of a fifth embodiment of the present invention, in which 50 is a clock driver, 51.
52.53 is a gate that constitutes a master latch, 52.5
4.55 is a gate that constitutes a slave latch, 56.5
7 is a gate added as necessary when increasing input data. In this example, 52 is the common gate.

The embodiment shown in FIG. 11 is slightly different from the embodiment shown in FIG.
It is a modified version.

FIG. 12 is a circuit block diagram of a sixth embodiment of the present invention, in which 60 is a clock driver, 61.
62.63 is a gate that constitutes a master latch, 62.6
4.65 is a gate forming a slave latch. In this example, 62 is the common gate.

The embodiment of FIG. 12 is similar to the embodiments of FIGS. 2 and 9, except that the clock input of the latch gate 64 of the slave branch is led from the input side of the clock driver 60. are different.

FIG. 13 is a circuit block diagram of a seventh embodiment of the present invention, in which 70 is a clock driver, ? 1.
72.73 is a gate that constitutes a master latch, 72.7
4.75 is a gate that constitutes a slave latch, 76.7
7 is a gate added as necessary when increasing input data. In this example, 72 is the common gate. The embodiment of FIG. 13 is similar to the embodiment of FIG. 1O, except that the clock input of the latch gate 74 of the slave latch is guided from the input side of the clock driver buffer 0.

FIG. 14 is a circuit block diagram of an eighth embodiment of the present invention, in which 80 is a clock driver;
82.83 are gates forming the master latch, 82,8
4.85 is a gate that constitutes a slave latch, 86.8
7 is a gate added as necessary when increasing input data. In this example, 82 is the common gate.

The embodiment of FIG. 14 is similar to the embodiments of FIGS. 1 and 11, except that the clock input of the latch gate 84 of the slave latch is guided from the input side of the clock driver 80. different.

Figure 15 shows Figure 1, Figure 2, Figure 9, Figure 10, Figure 1.
2 is a diagram illustrating an example of the operation of the clock driver CD shown in FIG. 1. FIG. In Figure 15, CLK is the input clock, sin is the sample signal, HD is the hold signal, and tG is the gate 1.
The approximate delay of a stage, ts, is a skew value. In this example, LIP/
Each tG and t3 of down etc. may not be the same.

FIG. 16 is a diagram illustrating an example of the operation of the clock driver CD' shown in FIGS. 12, 13, and 14. Components with the same symbols as in FIG. 15 have the same names. In the configurations of FIGS. 12, 13, and 14, the clock driver CD shown in FIG. 15 may be used instead of the clock driver CD' shown in FIG. 16. Furthermore, when the clock driver CD' shown in Fig. 16 is used in the configuration examples shown in Figs. 12, 13, and 14, the skew value of the leading edge of the clock driver is determined by the passage time of one stage of the clock driver. Since there is no leading edge skew, the master latch speed is improved.

FIG. 17 is a diagram showing an example of the circuit of the clock driver CD, and FIG. 18 is a diagram showing an example of the waveform of the clock driver CD. In FIG. 17, when resistors RC51° and RC32 are not added, the sample signal is SM.

The hold signal HD changes as shown by the broken line in FIG. 18, but it changes so that the resistors RC3I and RC32 are added. This is because the current flowing through the differential transistor is a constant current, so an additional voltage drop occurs due to the added resistance, and the result is SM.

This is because it appears on HD. In both SM and HD, the rise of the waveform is delayed, which results in a skew time ts.

Incidentally, in the case where the rise is delayed by SM as shown in FIG. 16, the resistor RC31 may be deleted from the circuit shown in FIG. 17.

〔Effect of the invention〕

As can be seen from the drawings and explanations of the embodiments above, the present invention has the advantage of preventing racing, reducing the number of gates, and increasing the density of the circuit.

[Brief explanation of drawings]

Fig. 1 is a circuit block diagram of the first embodiment of the present invention, Fig. 2 is a circuit block diagram of the second embodiment of the invention, Fig. 3 is a time chart diagram of Fig. 1, and Fig. 4 is a circuit block diagram of the second embodiment of the invention. FIG. 5 is a circuit example diagram of gates 16, 17, and 18. FIG. 6 is a block diagram of a conventional latch circuit. FIG. 7 is a block diagram of a conventional master-slave branch circuit. The figure is a time chart diagram of FIG. 7, FIG. 9 is a circuit block diagram of a third embodiment of the present invention, FIG. 10 is a circuit block diagram of a fourth embodiment of the present invention, and FIG. 11 is a circuit block diagram of a fourth embodiment of the present invention. 12 is a circuit block diagram of the sixth embodiment of the present invention, FIG. 13 is a circuit block diagram of the seventh embodiment of the present invention, and FIG. 14 is the circuit block diagram of the seventh embodiment of the present invention. A circuit block diagram of the eighth embodiment of the invention. FIG. 15 is a diagram for explaining an example of the operation of the clock driver CD. FIG. 16 is a diagram for explaining an example of the operation of the clock driver CD'. FIG. 17 is a diagram for explaining an example of the operation of the clock driver CD. FIG. 18 is a diagram showing an example of a circuit of a clock driver CD. FIG. 18 is a diagram showing an example of a waveform of a clock driver CD. In the figure, CD, CD' are clock drivers, 1, 2 . 1°, 2', 16 is OR gate, 3,
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Claims (2)

[Claims] (1) In a master slave latch circuit consisting of a master latch that outputs a master output signal and a slave latch that outputs a slave output signal, the latch gate of the master latch is configured to be shared as the data gate of the slave latch. Features a master-slave latch circuit. (2) A clock driver gate that outputs a positive phase clock and a negative phase clock, a data gate that inputs the output clock and data signal of one of the clock driver gates, and a clock driver gate that outputs the output clock of the other clock driver gate and the master. a first latch gate that inputs an output signal; a master output gate that inputs the output of the data gate and the output of the first latch gate and outputs a master output signal; and an input clock to the clock driver gate. Or, a second circuit whose one output clock of the clock driver gate is one input and the slave output signal is the other input.
and a slave output gate which takes the output of the first latch gate as one input, takes the output of the second latch gate as the other input, and outputs a slave output signal. A master slave latch circuit according to claim (1).