JPS62202527A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To control surface-defect density generated in an element active region at a constant value by using the ratio of an absorption coefficient alpha1106 in a wave number of 1106cm<-1> resulting from interstitial oxygen in single crystal silicon to that in a wave number of 513cm<-1> resulting from substitutional type oxygen as a monitor for the generation of minute defects in an silicon semiconductor wafer. CONSTITUTION:When the absorption coefficients of infrared beams of 1106cm<-1> and 513cm<-1> before heat treatment are each represented by alpha1106 and alpha513 and relationship with internal minute-defect density to the k value = alpha1106/alpha513 of the absorption coefficients is taken, internal defect density extends over 2X10<8>cm<-3> or less in a sample having k<4.5, but surface dislocation density (a pattern-end dislocation generation rate) is also lowered when it is kept within the range. Accordingly, when an element formation process consists of a heat treatment process of 1,000 deg.C or less as seen in an nMOS having no well process, the generation of internal minute defects is inhibited by specifying the k value of an silicon wafer and holding k<4.5, thus preventing the generation of a surface dislocation.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device, and more specifically, a method for eliminating micro defects on the surface of a wafer or micro defects inside the wafer that occur during a device process. This invention relates to an improved method of manufacturing a semiconductor device based on a method of predicting defects from the infrared absorption characteristics of a wafer.

(Prior Art) Usually, the quality of silicon wafers used as substrates for mounting semiconductors such as LSIs is focused on dopant species, resistivity, oxygen content, carbon content, oxidation-induced stacking faults, and the like.

Incidentally, most silicon wafers are cut from single-crystal ingots pulled and grown using the Czochralski (CZ) method, but since the CZ method uses a quartz crucible, the oxygen content is 5 to 13 C1m3
Most of the supersaturated oxygen exists between the lattices of the silicon single crystal. Therefore, the infrared absorption method is generally used to measure the oxygen concentration, and the absorption coefficient at room temperature at 1106c, which is the absorption wave number of interstitial oxygen
1] is falsified by the following equation (I).

[Oi] = 3.01 XIO” Xα1.es
atoms/cnt”...(I) Firstly, as is well known, this supersaturated oxygen content causes micro defects such as oxygen precipitates and dislocations to form when subjected to heat treatment at temperatures below 1000°C in the device process. At the same time, they become a source of oxidation-induced stacking faults (O8F) and dislocations at pattern edges due to micropattern distortion.When these microdefects, O8F, and dislocations are introduced into the device active region, p-n This causes junction leakage, poor memory retention time, etc., and significantly reduces the yield of LSI.

Therefore, conventionally, by using a silicon wafer whose oxygen content is defined according to the process of the LSI device to be manufactured, micro defects are prevented from being introduced into the device active region. For example, dynamic memory (DRAM)
IX 10” atom for n-channel MOS device
A CZ wafer with a relatively low oxygen content of less than s /CI' is used. Note that if the oxygen content is too low, the wafer will become mechanically weak and warp will occur during the process, increasing the defective rate.
/ C112 or higher.

However, as mentioned above, the contained oxygen concentration is 5 to IOX.
Even with the conventional method of defining a certain range such as 10'' atols/C13, the density of microdefects in the surface active region does not become constant.

The reason for this is thought to be that the density of microdefects is affected not only by the concentration of oxygen contained, but also by the stability of the solid-liquid interface during crystal growth, thermal history, and other residual impurities (e.g. carbon). However, even if these conditions are further controlled, the defect density may not be sufficiently controlled. Therefore, in order to actually determine the suitability of a wafer, a simulation is performed in which sampled wafers are subjected to the same heat treatment as in the manufacturing process and the defect density that occurs is evaluated. However, because of this, there was a problem in that it caused a significant increase in cost.

Second, as is also well known, micro-defects due to oxygen precipitation are generated in high density inside the wafer and contribute to gettering, and are also eliminated by high-temperature heat treatment near the wafer surface. Intrinsic gettering (IG) is used to form a defective region and an element is formed in the defect-free region.
) is used as a technology.

For example, in the process of bipolar devices, the buried diffusion step and epitaxial growth step are usually in the early stages of the process, so the oxygen concentration is 9.5×10”.
Before introducing silicon wafers of atoms /C1113 or higher into the process, we perform low-temperature heat treatment to form oxygen precipitation nuclei, and use high-temperature diffusion and epitaxial processes to outwardly diffuse oxygen and nuclei near the surface of the sea urchin. After forming a defect-free layer near the surface, epitaxial growth is performed. The same holds true for the OMOS element process, and the well formation process corresponds to the buried diffusion process and the high temperature heat treatment of the epitaxial growth process in the bipolar element process.

The method exemplified above is a single-stage heat treatment method in which low-temperature heat treatment is performed before device processing, but multi-stage heat treatment methods such as low-temperature heat treatment - high temperature heat treatment, high temperature heat treatment - low temperature heat treatment - medium temperature heat treatment, etc. are also adopted before device processing. has been done.

However, in the conventional IG method described above, even if the same oxygen concentration range is specified for the wafer, the width of the surface defect-free layer and the internal defect density often differ, and the IG effect always exceeds a certain level. Therefore, it has been difficult to predict product yield at the wafer stage before processing.

In the present invention, we will focus on the absorption coefficient at an infrared wave number of 513c "1," but conventionally it was known that the absorption at a wave number of 513c "1" was only due to absorption by substitutional oxygen in silicon (17th Conference on SO
f 1d3tate[)evicas andMate
Rials, Tokyo, 1985゜p291-29
(see 2).

(Problems to be Solved by the Invention) An object of the present invention is to provide a method for manufacturing a semiconductor device in which the density of surface defects generated in an element active region in a silicon device process is controlled to be constant. Another object is to provide a method for manufacturing a semiconductor device in which the effect of intrinsic gettering is controlled to a constant level in the process. Another object of the present invention is to provide a method for manufacturing a semiconductor device, etc., in which the characteristic yield of the semiconductor device in the process can be predicted at the wafer stage before inputting the process.

[Structure of the Invention] (Means for Solving the Problems) The present invention uses an infrared absorption method to calculate the absorption coefficient αn at a wave number of 1106 cr1 caused by interstitial oxygen in single crystal silicon and the wave number caused by substitutional oxygen. 513c "Based on a new method in which the ratio (α77./α, 1.) with the absorption coefficient α51. at 1 is determined and the ratio (hereinafter referred to as k value) is used to monitor the occurrence of micro defects in silicon semiconductor wafers. It is.

The first invention is a method for manufacturing a semiconductor device in which elements are formed on a silicon substrate with a k value of 4.5 or less at a processing temperature of 1000° C. or less. The first invention is particularly suitable for forming an n-type MOS device without a well process.

A second invention is a method for manufacturing a semiconductor device, which includes forming a device on a silicon substrate having a kgb of 4.0 or more, including a high-temperature heat treatment process at 1100° C. or more. The second invention is 110
This method is particularly suitable for forming bipolar devices, which perform a buried diffusion process of group V groups, followed by an epitaxial growth process, or OMOS devices, which perform a well process as a heat treatment process at 0° C. or higher.

(Function) In the first invention, the ratio of the absorption coefficient at wave number 1106 cn+-1 to the absorption coefficient at wave number 5130 Im-1 is α7. e.

/α513, that is, has a positive correlation with the internal microdefect density, so if devices are formed at a low processing temperature of 1000°C or less on a wafer with a k value of 4.5 or less, there will be no damage to the device active region. The generation of micro defects is suppressed, and devices can be formed with virtually no defects.

The above operation in the first invention will be explained in more detail.

3 plants grown using C7 method 12511IIllφ (7)
(100) Cut out a wafer from a silicon single crystal rod and measure wave numbers of 1106 cr' and 513 cm using infrared absorption method.
-' absorption coefficient was measured. The oxygen concentration [Oi] was calculated from the absorption coefficient at a wave number of 1106 cm by formula (I) and found to be 5 to 10 x 1017a0IIS/Cl11
It was in the range of 3. Silicon nitride MrQ is partially formed on these silicon wafers, and using this as a mask, heat treatment is performed at 1000° C. for 8 hours in an oxygen atmosphere to form a field oxide film. The oxide film and nitride film on the Enoki surface were completely peeled off, the surface was light etched, and dislocations occurring at pattern boundaries were observed using an optical microscope. Furthermore, the wafers were squared on the (011) plane, and the cleavage plane was light etched to investigate the density of minute defects occurring inside the wafers.

The incidence of dislocations on the surface can be determined by
The relationship between the internal microdefect density and the dislocation generation rate is shown in FIG. 1 when expressed as the percentage of chips in which dislocations have occurred among the chips arranged in a flat vertical direction. In other words, as shown in Figure 1, as the internal microdefect density increases, dislocations occur on the surface and the dislocation generation rate becomes thicker. Since it becomes a cause of defects, it can be seen that the higher the internal microdefect density, the higher the element failure rate, which affects the yield.

By the way, the internal microdefect density was conventionally said to depend on the interstitial oxygen concentration and carbon concentration, but in the case of this sample, all carbon is below the detection limit, so the internal microdefect density depends on the interstitial oxygen concentration. There must be a correlation. However, the actually measured relationship between the interstitial oxygen concentration and the microdefect density is as shown in FIG. 2, and no clear correlation can be seen. In other words, interstitial oxygen and carbon concentrations alone can cause internal micro-defects! It is impossible to predict the degree.

Therefore, as in the present invention, 1106c'' before heat treatment is used.
The absorption coefficient of infrared light of 1 and 513 cr' is C
If we take the relationship between the internal microdefect density and the value -α,6/α6,3 as 1,α513, the result will be as shown in FIG. That is, for samples with k < 4.5,
Although the internal defect density is below 2X 10"cr', the surface dislocation density is also low at that point, as shown in Figure 1. Therefore, the element formation process is required as in nMOS without a well process. When it consists of a heat treatment process at 1000°C or less, the value of the silicon wafer is defined and k<
By setting the value to 4.5, the occurrence of internal micro-defects is suppressed, and as a result, it is possible to prevent the occurrence of surface dislocations.

In the second invention, the wafer's n value is set to 4.0 or higher to increase the internal microdefect density, which has a positive correlation with it, and the surface is free from defects for forming elements by outward diffusion during the heat treatment process at 1100°C or higher. Forming a region and stabilizing I
This is to bring out the G effect.

The above operation in the second invention will be explained in more detail.

As shown in Fig. 11, the oxygen-containing S produced by the CZ method
degree 7~10X 10" atoIlls/C13, contained carbon m III is the detection limit (2x 10" atom
s/am”) below, boron-doped resistivity 2~
For a P-type silicon wafer 1 of 6ΩC1, absorption coefficients αn, 1106a ``1 and 513 cm-'', respectively, were obtained by infrared absorption method.

C513 was measured. Arsenic is partially embedded and diffused into this silicon wafer 1 at 1200°C to form an N+ buried layer 2, and an N-type epitaxial layer 3 is roughly formed to a thickness of about 10 μm.
About 1 was formed. This silicon wafer was subjected to an oxidation heat treatment at 1000° C. for 16 hours in an oxygen atmosphere, and O8F generated on the surface 3a of the epitaxial layer was exposed by an etching method and cross-sectionally observed using an optical and optical microscope. Observed O5F
The density is plotted against the oxygen concentration as shown in FIG.

That is, there is no clear correlation between the O8F density and the oxygen content concentration.

On the other hand, when the correlation between O8F density and k value (αI1.l/α, 1.) is taken, it is as shown in FIG. That is, for wafers with k<4.5, O8F
Densities range from almost 0 to the order of 10' am-2, but for wafers with k≧4.5, the density is as small as 50 cm-2 or less, allowing efficient IG and high-quality epitaxial production. It can be seen that layers are formed.

<Example> A first embodiment of the first invention will be described.

As a first example, after slowly cooling the ingot pulled into the growth furnace of the C2 method, a heater is attached, and the tail is heated to 850°C so that the value of the tail becomes 4.5 or less, especially immediately after the formation of the tail. A wafer was cut from one ingot that was slowly cooled at ~550°C for 4 hours. For the wafer from the seed end to the tail, the k value, the lattice interval 1' [I element ai 1 degree, 1000°C,
The internal microdefect density after 16 hours of heat treatment was measured, and the results shown in FIG. 6 were obtained.

As a control example, the k value, interstitial oxygen concentration, and internal micro defects were measured for a wafer cut from a single ingot grown by the normal C7 method without adding a post-heater, and the results shown in Figure 7 were measured. Got the results.

Looking at the tail region where many micro-defects occur in the control example (Figure 7), we can see that there is a better correlation with the micro-defect density.
Lattice I! It can be seen that it is not the lWI elementary density but the k value. Therefore, by using the k value as a monitor, CZ
If the thermal history program for pulling the process ingot is set as in the first embodiment, the density of micro defects on the wafer surface can be suppressed and controlled to be constant (FIG. 6).

As a second embodiment of the first invention, one grown as in the first embodiment, one grown by the normal C7 method, 3
Cut out a wafer with an oxygen concentration of 5 to iox io''atoms/am' from a 125 mmφ (100) silicon single crystal rod, and combine it with a group of wafers with an oxygen concentration of ≦4.5.
The wafers were divided into groups with k>4.5. Both groups of wafers are
When it was put into the MOSLSI process, k≦4.
The group with k>4.5 had a good average yield of 63%, while the group with k>4.5 had an average yield of 42%. When the cause of the defect was investigated, it was found that dislocations had occurred on the wafer surface, resulting in bit defects. Incidentally, when we investigated the relationship between the wafer's n value and the dislocation generation rate, we found that the dislocation generation rate increased rapidly when k > 4.5, as shown in Figure 8. Examining the relationship with the occurrence rate, we found that the internal microdefect density was 2 as shown in Figure 9.
The dislocation occurrence rate increases rapidly above X 10'' Cl-3.

In addition, 256kD RAM fabricated from wafers with values of 3.9, 4.4, 4, 6, and 4.8 were heat-treated at 175°C for up to 1000 hours, and the dependence of memory retention time characteristics and heat treatment time was investigated. When we investigated the reliability in order to determine the
It shows a retention time of about c, but those with k values of 3.9 ((a) in the figure) and 4.4 (b), that is, ≦4.5, are 1.
There is no change even after 000 hours, but the k value is 4.6 (c),
4.8(d), that is, those with k>4.5 gradually deteriorated and their reliability decreased.

As a third embodiment according to the second invention, an oxygen content of 7 to 10 x 10" atoms/c was produced by the Cl method.
e', the concentration of carbon contained is at the detection limit (2X1016 atoms
Using a P-type silicon wafer (resistivity 2 to 6 ΩC) with k≧4.5 (resistivity: 2 to 6 ΩC), an N1 buried layer and an N-type epitaxial layer were formed at 1200°C at 1200°C. A bipolar IC was fabricated on the layer.On the other hand, as a control example, the oxygen concentration was 29.5×10
” atoms /C1l' or more, the carbon concentration is less than the detection limit (2X 10” atoms /Cm3), k
<4.5 P-type silicon wafer (resistivity 2~6Ωc
A bipolar IC was produced using the method.

When the yield of the IC was examined based on the V-■ characteristics of the bipolar transistor in this IC, the average yield of the third embodiment, which was defined as k≧4.5, was as high as 70%; The average yield of the control example is 3
It varied between 8 and 74%.

The main cause of the defective chip in this case is Ebitaxi 1? It was recognized that this was O8F that had occurred in the Le layer. That is, using a wafer with a k value of 4.5, temperature
When a bipolar element is formed by a process including heat treatment, the O8F density can be reduced as an effect of IG, and as a result, yield can be improved.

As a fourth embodiment of the second invention, three 12
Oxygen concentration 7.5-11.5x 10" atoms / Cl1 from (100) silicon single crystal rod of 5a + lφ
No. 13 N-type wafers were cut out, and boron well thermal diffusion was performed on the wafers at 1150° C. for 5 hours to produce MOS diodes.

On the other hand, as a control example, plants were grown using the conventional CZ method in which the k value varied from 2.8 to 5.0, and the oxygen concentration was 1.5 to 11.5 x 10.
A MOS diode was fabricated in the same manner as in the fourth embodiment using an N-type wafer of "atols/cm'.

The MOS diodes of the fourth example all had generation lifetimes of 300 μsec or more, but the MOS diodes of the target examples showed values that varied from 50 to 300 μsec.

Furthermore, FIG. 12 shows that in the tests of the fourth example and its target example, very favorable results were obtained by specifying the oxygen concentration in addition to the k value. Figure 12 shows the k value and O8
This is a diagram showing the correlation with F density. In the diagram, the points plotted with Q marks indicate oxygen concentration of 7.5 to 11.5X 1
Points in the group defined in the range of G'' atoms /CI' Incidentally, the points in the fourth example are points with a 0 mark where kfl[is 4.0 or more], and the points plotted with a - sign are M elements. Points in the group where the concentration exceeds 11.5x 101017ato/am3, points plotted with ・ are where the oxygen concentration is 7.5x
10" atoras 701.

As can be seen in the figure, the value is 4 to 5 and the oxygen concentration is 7.5 to 11.5 x 10” atoms/c.
By specifying m3, much better results can be obtained than by specifying only the k value as 4 to 5. In addition, the fact that it is preferable to specify 11 degrees of oxygen in addition to the k value was the same in the first to third embodiments.

It was also found to be effective to specify the carbon concentration within the detection limit of the infrared absorption method (2x 101016ato/cm3 or less) as in the above examples.

In the third and fourth embodiments, 1 in the device process
Heat treatment at 100°C or higher forms gettering nuclei inside the wafer and also forms a defect-free layer near the surface, so an IG effect similar to that achieved by complicated heat treatment steps in conventional processes can be achieved. Furthermore, it was also recognized that the 1G effect could be further improved if heat treatment was performed at 600 to 800°C before inputting into the device process.

[Effect of the invention] According to the present invention, the value (α17, /
α39. ) has been found to be able to control the occurrence of micro defects in device processes, and can be used extremely effectively in the manufacture of semiconductor devices. Its use can be considered in addition to the formation of a defect-free device active region and effective intrinsic gettering as pointed out in the main part of this specification, as required.

[Brief explanation of drawings]

Figures 1 to 3 are graphs explaining the first invention in detail, Figures 4 and 5 are graphs explaining the second invention in detail, and Figures 6 and 7 are the effects of the first embodiment. 8 to 10 are graphs explaining the effects of the second embodiment, FIG. 11 is a cross-sectional view of the device explaining a part of the device formation process in the third embodiment, and FIG. 12 is a graph explaining the effect of the second embodiment. It is a graph explaining the effect of the third example. 1... Silicon wafer, 2... Buried layer, 3...
-Epitaxial layer. Patent applicant: Toshiba Corporation Internal microdefect density (cr”) Fig. 1 Interstitial oxygen concentration (xlo” atoms/cm3) Fig. 2
Values shown in Figure 3 Figure 4 Values Figure 5 Figure 6 Figure 7 Values Figure 8 Internal micro defect density (CS-3) Figure 9 Figure 10 Figure 11 Values Figure 12

Claims (1)

[Claims] 1. Infrared wave number is 1106cm^-^1 and 513c
The absorption coefficient at room temperature at m^-^1 is α_1, respectively.
_1_0_6, α_5_1_3, α_1_1_
A method for manufacturing a semiconductor device, characterized in that n-type and p-type element regions and element isolation regions are formed at a formation temperature of 1000° C. or less using a silicon wafer having a ratio of 0_6/α_5_1_3 of 4.5 or less as a substrate. 2 Silicon wafer contains oxygen concentration 1×10^1^8a
The method for manufacturing a semiconductor device according to claim 1, wherein the toms/cm^3 or less. 3 Silicon wafer contains carbon concentration 2×10^1^6a
3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the toms/cm^3 or less. 4 Infrared wave number is 1106cm^-^1 and 513c
The absorption coefficient at room temperature at m^-^1 is α_1, respectively.
_1_0_6, α_5_1_3, α_1_1_
A method for manufacturing a semiconductor device, characterized in that element formation is performed using a silicon wafer having a ratio of 0_6/α_5_1_3 of 4.0 or more as a substrate and including a step of performing high-temperature heat treatment at 1100° C. or more. 5 The board is α_1_1_0_6/α_5_1_3 is 4
．． Claim 4, which is obtained by heat-treating a silicon wafer of 0 or more at a temperature of 600 to 800°C for 4 hours or more.
A method for manufacturing a semiconductor device according to section 1. 6 α_1_1_0_6/α_5_1_3 is 4.5 or more, and the high-temperature heat treatment step is a buried layer diffusion step of group III or group V impurities, and epitaxial growth is performed after the diffusion to form a bipolar element therein. 5. The method for manufacturing a semiconductor device according to item 4. 7 Silicon wafer contains oxygen concentration 7.5 to 9.5 x 1
7. The method of manufacturing a semiconductor device according to claim 6, wherein the amount is 0^1^7atoms/cm^3 or less. 8 Silicon wafer contains carbon concentration 2×10^1^6a
8. The method of manufacturing a semiconductor device according to claim 6 or 7, wherein the toms/cm^3 or less. 9. The method of manufacturing a semiconductor device according to claim 4, wherein the high temperature heat treatment step is a well forming step, and a MOS element is formed in the surface layer after the well is formed. 10 Silicon wafer contains oxygen concentration 7.5 to 11.5
10. The method of manufacturing a semiconductor device according to claim 9, wherein the amount is less than ×10^1^7 atoms/cm^3. 11 Silicon wafer contains carbon concentration 2×10^1^6
11. The method for manufacturing a semiconductor device according to claim 9 or 10, wherein the semiconductor device has a density of at most atoms/cm^3.