JPS62202256A - Peripheral bus confounding system - Google Patents

Abstract

PURPOSE:To reduce the number of connecting lines of both systems and prevent the trouble of a peripheral bus controller from causing the function stop of the other system by connecting a pair of peripheral bus devices to a pair of peripheral bus controllers of the other system through a pair of switching means. CONSTITUTION:A central controller 1a of a current system sets a current stand-by signal Sa to logical '1' through a processor bus 3a, and a central controller 1b of a stand-by system sets a current stand-by signal Sb to logical '0' through a bus 3b, and gates 67a and 67b are set to the conduction state and the cut-off state respectively. If an FF 65a is set to the separation mode, a mode ma is set to '0' and is transmitted to control circuits 66a and 66b, and transistors TRs 61a, 62a, 61b, and 62b and TRs 64a and 64b are set to the conduction state and the cut-off state respectively. Thus, central controllers 1a and 1b control peripheral devices 4a and 4b through the processor bus 3a, a peripheral bus 5a, and busses 3b and 5b. If the signal ma is set to '1', the confounding mode is set.

Description

[Detailed Description of the Invention] [Summary] In a redundant information processing system, an intersystem bus is provided between peripheral bus control devices of both systems, and the open/close state of switching means interconnecting the processor bus, the peripheral bus, and the intersystem bus is controlled. By controlling both systems of the duplex information processing system, it is possible to set both systems to a separation mode and a confounding mode.

[Industrial application field]

The present invention relates to an improvement in a peripheral bus confounding method in a redundant information processing system.

For example, in information processing systems that require high multiplicity, such as electronic switching equipment, the central control unit, main storage unit, and peripheral devices are each duplicated, with one operating as the active system and the other as a standby system. .

In operating such a redundant information processing system,
It is considered to configure a separation mode in which both systems are separated and made independent, and a confounding mode in which one central controller controls the peripheral devices of both systems.

In this type of duplex information processing system, there is a need for a means that has a small number of connecting lines in both systems and can prevent a failure in one system from spreading to the other system as much as possible.

[Conventional technology]

FIG. 3 is a diagram showing an example of a conventional peripheral bus confounding method in this type of duplex information processing system.

In FIG. 3, the central control device 1a and the main storage device
2a are connected by a processor bus 3a, and a plurality of peripheral devices 4a are connected by a peripheral bus 5a. Further, the processor bus 3a and the peripheral bus 5a are connected via a peripheral bus control device 6a, and one system (hereinafter referred to as the A system)
Configure.

Similarly, the central control device 1b, main storage device 2b, and peripheral device 4b are also connected by a processor bus 3b, a peripheral bus 5b, and a peripheral bus control device 6b, forming the other system (hereinafter referred to as the B system).

Further, the peripheral bus control device 6a is also connected to the processor bus 3b, and the peripheral bus control device 6b is also connected to the processor bus 3b.
connected to a.

The peripheral bus control devices 6a and 6b turn on the built-in bus transceivers (TR) 61a and 62a1 and 61b and 62b, respectively, and turn off the path transceivers 63a and 63b, so that the A system and the B system are placed in the separation mode. is set to

Further, when the central control device 1a is the active system and the central control device 1b is the standby system, the peripheral bus control device 6a turns on the path transceivers 6], a, and 62a, and cuts off the path transceiver 63a, and also performs peripheral bus control. Device 6
b makes the path transceivers 62b and 63b conductive;
By setting the path transceiver 6■b to the cut-off state,
The central control device la is set to a confounding mode in which it can also control the B-system peripheral devices 4b.

[Problem that the invention seeks to solve]

As is clear from the above description, in the conventional peripheral bus confounding method, in order to realize the confounding mode, the peripheral bus control devices 6a and 6b were directly connected to the processor buses 3b and 3a of other systems, respectively.

Therefore, the number of connection lines between the two systems increases, and there is a risk that a failure occurring in the peripheral bus control device 6a or 6b will immediately cause the other system to stop functioning.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 1a and lb are central control units, 2a
and 2b are main storage devices, 3a and 3b are processor buses, 4a and 4b are peripheral devices, 5a and 5b are peripheral buses, and 6a and 6b are peripheral bus control devices.

7 is an intersystem bus provided according to the present invention and connects the peripheral bus control devices 6a and 6b.

100a to 300a are opening/closing means provided according to the present invention and connect the processor bus 3a, peripheral bus 5a, and intersystem bus 7, and 100b to 300b are provided according to the present invention and are opening/closing means for connecting the processor bus 3a, peripheral bus 5a, and intersystem bus 7.
b and the intersystem bus 7.

[Effect]

The peripheral bus control device 6a controls the opening/closing means 100a and 200.
a is set to a conductive state, and the opening/closing means 300a is set to a cutoff state,
Further, the peripheral bus control device 6b is connected to the opening/closing means 100b and 2.
By setting 00b in a conductive state and opening/closing means 300b in a cutoff state, both systems are set in separation mode.

Further, for example, the peripheral bus control device 6a sets the switching means 100a to 300a to the transmission state, and the peripheral bus control device 6b sets the switching means 200b and 3OOb to the transmission state, and the switching means 100b to the cutoff state. is set to confounding mode.

That is, according to the present invention, since both systems are connected only by the intersystem bus 7, the number of connection lines is also reduced.

Further, the peripheral bus control devices 6a and 6b are connected to the peripheral bus control devices 6b and 6a of other systems via the intersystem bus 7, and are not directly connected to the processor buses 3b and 3a of other systems, so the peripheral bus control devices 6a and 6b are The possibility that a failure of the control device 6a or 6b will directly cause a malfunction of other systems is reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram illustrating a peripheral bus interlacing method according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, bus transceivers 61a, 162a and 64a, mode flip-flop (FF) 65a,
A control circuit (CTL) 66a and a gate 67a are provided in the peripheral bus control device 6a as opening/closing means 100a to 300a, and bus transceivers 61b, 62b and 64b, a mode flip-flop 65b, and a control circuit 6
6b and gate 67b are opening/closing means 100b to 300
b is provided in the peripheral bus control device lb.

In Fig. 2, the central control unit 1a set in the active system
is connected to the peripheral bus control device 6a via the processor bus 3a.
The active standby signal sa to be transmitted to the control circuit 66a of
The central control unit 1 is set to "1" and is also set to the standby system.
b is connected to the peripheral bus control device 6 via the processor bus 3b.
The active standby signal 5b transmitted to the control circuit 66b of the controller 66b is set to logic "0"-. Note that the working reserve signal sa set to the logic "1" makes the gate 67a conductive, and the working reserve signal 5b set to the logic "O" puts the gate 67b in the cutoff state.

In this state, when the mode flip-flop 65a is set to the separation mode, the output mode signal ma is set to logic "0" and is transmitted to the control circuit 66a, and is also transmitted to the control circuit 66b via the signal line 8. It is also transmitted to

The control circuit 66a is configured such that the transmitted mode signal ma is a logic “
0'', the path transceivers 61a and 62a; the Ici pre-notification state transceiver 64a are set to the cut-off state.

The control circuit 66b also controls the transmitted mode signal ma to be logic “
When it is determined that it is set to 0', the path transceivers 61b and 62b are set to the conductive state, and the path transceiver 64b is set to the cutoff state.

As described above, the central control device f 1 a can control the peripheral bag z4a via the processor bus 3a and the peripheral bus 5a, and the central control device 1b can control the peripheral bag z4a via the processor bus 3a and the peripheral bus 5a.
The peripheral device t 4 b can be controlled via the peripheral bus 5b, and the A system and B system are set to separate mode.

Next, when the central controller 1a is in the active system and the central controller 1b is in the standby system, and the mode flip-flop 65a is set to the confounding mode, the output mode signal ma is set to logic "1", It is transmitted to the control circuit FIB 66a and also to the control circuit 66b via the signal line 8.

The control circuit 66a is configured such that the transmitted mode signal ma is a logic “
When it is determined that the active standby signal sa is set to logic "1", the path transceiver 6
1a, 62a and 64a are set in a conductive state.

On the other hand, in the control circuit 66b, the mode signal ma to be transmitted is set to logic "1", and the active reserve signal 5b is set to logic "0".
”, the path transceivers 62b and 64b are turned on, and the path transceiver 6
1b is set to the cut-off state.

As described above, the central control unit 1a can not only control the peripheral device 4a via the processor bus 3a and the peripheral bus 5a, but also control the peripheral device 4b via the processor bus 3a, the intersystem bus 7, and the peripheral bus 5b. It becomes possible,
On the other hand, the central control device 1b is disconnected from the peripheral bus 5b, and the A system and B system are set to the confounding mode.

As is clear from the above description, according to this embodiment, the A system and the B system are connected only by the intersystem bus 7 and the signal line 8, so the number of connection lines is significantly reduced. Furthermore, even if a failure occurs in the peripheral bus control device 6b, by setting the bus transceiver 64a in the peripheral bus control device 6a to a cutoff state, a failure in the peripheral bus control device 6b can cause the system A to stop functioning. Fear will disappear.

Note that FIG. 2 is merely one embodiment of the present invention, and the configuration of the duplex information processing system, for example, is not limited to that shown in the figure, and many other modifications may be considered.
In either case, the effects of the present invention remain the same.

〔Effect of the invention〕

As described above, according to the present invention, in the redundant information processing system, the number of connection lines between both systems is significantly reduced, and since the peripheral bus control device is not directly connected to the processor bus of the other system, one peripheral The possibility that a failure in the bus control device will directly cause a failure in other systems is reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a peripheral bus interlacing method according to an embodiment of the invention, and FIG. 3 is a diagram showing an example of a conventional peripheral bus interlacing method.

Claims (1)

[Claims] A central control unit (1a, 1b) and a main storage device (2a, 2b) are connected by a processor bus (3a, 3b), and one or more peripheral devices (4a, 4b) are connected to each other by a peripheral bus (3a, 3b). (5a, 5b), and in which the processor bus (3a, 3b) and peripheral bus (5a, 5b) are connected via a peripheral bus control device (6a, 6b), An intersystem bus (
7), each processor bus (3a, 3b), peripheral bus (5a
, 5b) and the inter-system bus (7) are provided in each of the peripheral bus control devices (6a, 6b), and each opening/closing means (100a to 300a, 100b to 3
00b) By controlling the opening/closing state of the peripheral bus interlacing system, both systems of the duplex information processing system can be set to either a separation mode or an interlacing mode.