JPS62200917A - Data conversion method - Google Patents

Abstract

PURPOSE:To improve an arithmetic speed by executing arithmetic only to a word area in a register where a data is written possibly to omit useless arithmetic. CONSTITUTION:The arithmetic is executed only to a word area having the possibility of data write in two registers having plural word areas in the method using the registers to convert a data. An operation word location calculation circuit 113, a selector 114 and a register 115 are provided. The operation word location calculation circuit 113 is a circuit generating an operation word location DWN based on a value DPT in the pointer 103, the value DWN is a value changed sequentially vased on the value DPT and showing a maximum word area number having the possibility of data write in the register 107 at the present stage. That is, the word area having the possibility of data write is obtained in advance and the arithmetic is executed to the area only, then the useless arithmetic is omitted and the arithmetic speed is improved.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a data conversion method, particularly a method for converting pie fat data into BCD.
This invention relates to a data conversion method for converting data into data.

(Prior Art) Digital data is generally expressed as binary data, that is, binary numbers inside a computer, but is it different from the decimal numbers that we use on a daily basis? ! BCD data, that is, representation as a binary coded decimal number is sometimes used. FIG. 5 is a flowchart showing a conventional general method for converting binary data into BCD data, and FIG. 6 is a block diagram of a conversion device used in this method.

First, the configuration shown in FIG. 6 will be briefly explained. Now, considering an example of converting m-byte binary data to n-byte BCD data, the m-byte binary data to be converted is stored in register 100, the n-byte BCD data obtained by the conversion is stored in register 101, Each is stored. Two registers 106 and 107 and an adder 109 are provided to perform this conversion.

In this example, registers 106 and 107 are word areas with a capacity of 32 bits (in the figure, they are represented as four horizontally arranged blocks separated by 1 byte).
are arranged in multiple words with upper and lower digit relationships. That is, the carry from the MSB of the 0th word (the lowest word area in the figure) is transferred to the LSB of the 1st word and processed. On the other hand, the adder rA 109 has a function of adding 32-bit data together in this example. Counter 105 has a function of indicating the currently referenced word area among the plurality of word areas in registers 106 and 107. Thereafter, the value of the counter 105 is set to R.
CT, counter 105 in registers 106 and 107
The data in the word area indicated by RtJ (RCT)
and RV (RCT). For example, R
u(0) indicates 32-bit data stored in the 09th word of the register 106. Selector 108 is R
Data from either LJ (RCT) or RV (RCT) is selected and applied to adder 109 . Since the other input of the adder 109 is always given RV (RCT), the adder 109 is connected to the selector 108.
Two types of addition can be performed by selecting . That is, RU (RCT) + RV (RCT)'j6 operation,
Either one of the calculations R゛V(RCT)+RV(RCT) can be performed. This addition result ADD is RV
(RCT) is written to register 107 as the new value of (RCT).

Note that the carry generated as a result of the operation is transferred to flip-flop 1.
10 is temporarily held as FCRY. Selector 111
When the adder 109 performs the 09th addition, O is added, and when the adder 109 performs the addition after the 1st word, it adds the carry FCRY value generated by the addition of the next lower word! ! 1109 LSB.

The m-byte binary data in the register 100 is sequentially taken in by predetermined bits from the most significant digits and converted into BCD data. In this example, in order to capture the upper 4 bits at a time, the m-byte data in the register 100 is transferred to the selector 102, which consists of cells of 4 bits each, and the pointer 103 indicates up to which cell the data has been fetched. It looks like this. The captured 4-bit binary data ZBNY is converted into 5-bit BCD data ZBCD by conversion 1104, and is stored in register 0.
It is written in the 0th word of 6. At this time, one word area of register 06 consists of 32 bits, so the lower 5 bits are ZBCD1 and the upper 27 bits are 0.
Bit data DBCD will actually be written. Further, the value -1 obtained based on the number of bytes n-〇- of the register 01 is stored in the register 12. As will be described later, the number of various operations will be controlled by this value.

Next, the procedure of the conventional conversion method will be described with reference to FIG.

First, in step S1, the values of counter RCT and pointer DPT are initialized, that is, set to O. Next step S
2 and S3, each word area of registers 106 and 107 is initialized, that is, set to 0. That is, first, all 32 bits of the Oth word of both registers are set to 0 as RCT-0.
Then, RCT is sequentially updated one by one until RCT≧('--1), and necessary word areas are initialized. Here, the value -1 is the value stored in register 12 as described above, and corresponds to the value obtained by subtracting 1 from the number of word areas used in the calculation.In this example, 1 word in registers 06 and 107 The area is 32
Consists of bits, that is, 4 bytes, so n-byte BCD
To obtain data, one word area is required. Therefore, a word area from the 0th word to the (-T--1)th word is required, and step s2. This necessary word area will be initialized by s3.

Next, in step S4, RCT is initialized to O again, and in step S5, DBCD is set to RlJ(0), that is, register 06.
Write in the 0th word of Here, in DBCD, as mentioned above, the lower 5 bits are BCD data ZBCD, and the upper 2 bits are BCD data ZBCD.
This is 32-bit data with 7 bits consisting of 0. In the end, among the m bytes of binary data in register 00, the top 4 indicated by the pointer o p -r -o
The data ZBNY of the pin is converted into 5-bit BCD data ZBCD by the converter 104, and written to the lower 5 bits of the O-th word of the register 106.

Subsequently, in steps S6 and S7, the registers 106 and 107 are added together. Adder 109 is 32
Since only bit width addition is possible, addition is performed sequentially from the O-th word to the (E-1)th word, taking into account carry, and the result is stored in register 07 as 1. Initially, ZBCO is written in the lower bit of RU (0), then other bits of RU (0) and RU (1)
Since L- to RU(-1) and Rv(0) to 10-RV(-1) are all O, this step S6
And the execution of S7 adds Z to the lower 5 bits of RV (0).
It only results in copying the BCD.

Next, the next 4 bits are fetched from the m-byte binary data in register 00. That is, step S8
At , the value of pointer DPT is updated by 1, and counter RCT is updated to 0.

When DPT-1, that is, the second capture is performed, the captured 4-bit binary data ZBNY is transferred to converter 1.
04t” is converted into 5-bit BCD data ZBCD.

Subsequently, in steps S10 to s21, the data RV in the register 107 is multiplied by 16.

That is, the operation of finding RV+RV using the adder 109 and using this as a new RV is performed four times. This allows data RV in register 07 to be multiplied by 16. In addition,
Since the adder 109 can only add 32 bits wide,
Each addition operation is performed sequentially from the 0th-"L-th word to the (-1)th word, taking into account carry.

When this 16-fold operation is completed, the process returns to step 5 again. That is, the new C converted by the converter 104
Data DBCD, in which the lower 5 bits are D data ZBCD and the remaining 27 bits are O, is written to the 10th word of the register 106 as a new RLJ (0).

-This writing erases the old data of the 09th-th card. Now, in this state, the data RV of register 107
is the 8CD data corresponding to the upper 4 bits of the binary data to be converted, and is the 09th-
The third data RLI corresponds to the next highest 4 bits.
This is CD data.

In other words, RV has a weight of 4 bits compared to RU. However, since RV is a value multiplied by 16 in each of the above-mentioned steps, it has a weight equal to these 4 bits.

Therefore, in the additions in steps S6 and S7, the additions are performed in consideration of this weight.

In this way, data is fetched from register 100 in 4-bit increments and converted to BCD data.
07, RV is multiplied by 16 to give it weight, and the next 4-bit data is taken in and the same process is repeated.

Data is fetched in units of 4 bits, [111]-bytes, so 2m times of fetching is required to complete fetching of m bytes of data. If 2m times of acquisition have already been completed, that is, if DPT=(2m-1), the process ends in step s9. At this point, data RV in register 07 is transferred to register 01.
This is the desired BC() data.

(Problems to be Solved by the Invention) However, the above-described data conversion method has the disadvantage that the calculation speed is slow because it includes unnecessary calculations. This wasteful calculation is performed in step S in the flowchart of FIG.
6 and S7, and the 1.6 times operation in steps S10 to S21. The above addition operation is RU (RCT) + RV (RC
T) until ROT-0-RCT-(knee 1),
Above 16 times operation & tRV (RCT) + RV (RCT
) is repeatedly performed from ROT-0 to RCT-(upper-1). In other words, operations are performed sequentially from the 0th word to the (-L-1)th word of registers 06 and 107 while taking carry into consideration.

However, although the rIi calculation for the 09th word always has meaning, the calculations for the first and subsequent words become meaningless at the initial stage of the calculation. That is,
The first data entered after the first word is due to a carry from the lower word, so for example, the first word starts to perform meaningful operations when the zeroth word overflows. This is after the carry is included in the calculation. Until then, we will continue to perform meaningless operations such as adding O's.

As described above, the conventional data conversion method includes unnecessary calculations, which causes problems when the calculation speeds are close.

Therefore, an object of the present invention is to provide a data conversion method that can eliminate unnecessary calculations and further improve calculation speed.

(Structure of the Invention) (Means for Solving the Problems) A feature of the present invention is that in a method of performing data conversion using two registers each having a plurality of word areas, it is possible to write data in the registers. This is an attempt to improve the calculation speed by performing calculations only on word areas with certain characteristics.

(Function) As described as the problem to be solved by the invention, the conventional data conversion method has the drawback of performing meaningless and wasteful calculations. Here, the criterion for determining from which point to which word area a meaningful *0 is performed is controlled by the value of the pointer DPT. This will be explained using FIG. Assume now that m bytes of binary data are stored in the register 100 as shown in the figure.

In FIG. 3, it is assumed that each cell of the register 100 represents a data area of 4 bits each. Therefore each cell has DP
Corresponds to 0 to 2m-1 of T. Here, first, DPT=5
, that is, consider the calculation at the time when the sixth acquisition is performed. In this case, the maximum value (2') of 6 binary data is captured. (2'> 6= (2
8) Since it is 3, this binary data will definitely fit within the 3-byte data area. By the way, BCD
Since data can represent the number of degrees up to 102 in one byte, even if this binary data is converted to BCD data from the relationship (2) <(102)', it will always fit within the 4-byte data area. . That is, DPT
It can be seen that in the addition n operation up to -5, data is written only to the 0th word, and no data is written after the 1st word.

Further, considering the calculation at the time of DPT-12, that is, the 13th capture, the maximum value of the captured binary data is (24)13.

(2) From the relationship <(102)', even if this binary data is converted to BCD data, it will always fit within the 8-byte data area.

In this way, by determining in advance word areas where data may be written and performing calculation operations only on these areas, it is possible to eliminate unnecessary calculations and improve calculation speed. .

(Example) The present invention will be described below based on an illustrated example. 1st
The figure shows binary data to BCD according to an embodiment of the present invention.
FIG. 2 is a flowchart showing a method of converting data into data, and FIG. 2 is a block diagram of a converting device used in this method.

First, the configuration of the apparatus shown in FIG. 2 will be briefly described.

Note that the same components as those of the conversion device used in the conventional method shown in FIG. 6 are designated by the same reference numerals, and the explanation thereof will be omitted. The feature of this device is that the calculation word position calculation circuit 11
3. A selector 114 and a register 115 are newly provided. i! The word position calculation circuit 113 calculates the calculated word position D based on the value DPT in the pointer 103.
This is a circuit that generates WN. This value DWN is a value that changes sequentially based on the value DPT, and at this stage, register 1
07 indicates the maximum word area number in which data may be written.

As explained in FIG. 3, in addition operations up to DPT-5, meaningful operations are performed only on the 0th word,
In addition operations up to DPT-12, meaningful * operations are performed only on the first word. However, since the subsequent 16x operation requires even more data area, considering the word area where meaningful operations are performed through this addition operation and 16x operation, up to DPT-4, the 09- It is only necessary to perform calculations on the DPT-11
It can be seen that vII:[ has to be performed only for the first word. That is, until DPT=4, DWN-0, D
DWN-1 roars up to PT-11. Such a relationship is shown in the diagram of FIG. The operation word position calculation circuit 113 may be constructed of a ROM having a table as shown in FIG. 4, for example. Alternatively, a circuit that performs the same function as the table shown in FIG. 4 may be constructed by combining predetermined logic circuits. In short, any circuit may be used as long as it has the function of inputting DPT and outputting DWN corresponding to it.

The selector 114 inputs this DWN and the number of bytes n of the register L101 (-1), and outputs the smaller one as the ZWDN. The current value WDN of this ZWDN is stored in the register 15. As described later, various arithmetic circuits use this value WDN.
will be controlled by.

Next, the procedure of the conversion method according to the present invention will be described with reference to FIG. Note that steps that are the same as those in the flowchart of the conventional method shown in FIG. 5 are given the same reference numerals and explanations will be omitted. The difference from the conventional step is step 64' with a dash.

s7', s8', s11', s14', s17
'.

It is 520'. First, in step S4', a new operation for loading the value ZWDN into the register 15 is added in order to initialize the value WON in the raster 115. Further, the value WON in this register 15 is updated every time DPT is updated in step sQI. Step s7' is a step of specifying a word area in which an addition operation is to be performed, and the operation is repeated from the 0th word to the WDN word. In the conventional method, the 09th
The operation was performed from the - word to the (upper -1) word, but
According to this method, calculations are performed up to the WON word for which there is a possibility that data will be written at that point, and unnecessary calculations thereafter can be omitted.

Steps s11', s14', s17'.

S20' is a step of specifying the word area in which the 16x operation is to be performed, from the 0th word to the WD
The calculation is terminated after reaching N words, and unnecessary calculations can be omitted.

In this way, the addition operation and the 16x operation can be performed using the DPT-2.
This is repeated until m-1 is reached, and the final value in register 107 is transferred to register 101 as the BCD data to be determined.

Note that in the above embodiment, an example of converting binary data to BCD data was explained, but the present invention is not limited to this, and in short, data conversion is performed using two registers each having a plurality of word areas. Any data conversion method can be applied as long as it is a data conversion method.

In addition, in the above embodiment, unnecessary operations are omitted in both the addition operation and the 16x operation, but even if only one of them is omitted, the operation speed is sufficiently improved compared to the conventional method. can be achieved.

(Effects of the Invention) As described above, according to the present invention, in a method of performing data conversion using two registers having a plurality of word areas, operations are performed only on word areas in which data may be written in the registers. Because I decided to do this,
It is possible to omit unnecessary calculations and improve calculation speed.

[Brief explanation of drawings]

FIG. 1 shows B from binary data according to an embodiment of the present invention.
FIG. 2 is a block diagram showing an example of a device for performing the method shown in FIG. 1. FIG. 3 is an explanation showing the basic principle of the present invention. Figure 1 shows the table used to perform the method shown in Figure 5.
A flowchart showing a data conversion method to D data, and FIG. 6 is a block diagram showing an example of an apparatus for carrying out the method shown in FIG. S1 to s21... Each step of the flowchart, 100...
Register for storing binary data to be converted, 1
01...Register for storing BCD data obtained by conversion, 102...Selector, 103...Pointer, 104...Converter, 105...Counter, 1
06.107...Register having multiple word areas, 108...Selector, 109...Adder, 110
...Flip 70 knob, 111...Selector, 11
2...Register, 113...Arithmetic word position calculation circuit, 114...Selector, 115...Register.

Claims (1)

[Claims] 1. A first register in which b words of a word area having a capacity of a bits are arranged with upper and lower digits, and a second register having the same configuration as the first register. , an adder capable of performing addition of a-bit data, and a converter that converts c-bit binary data to d-bit data in a predetermined format. a first step of converting into d-bit data with a converter and writing the converted data into a lower word area of the first register; and a correspondence between the first register and the second register. adding the data in the word area to each other using the adder so that the carry is transferred to the upper word area,
a second step of writing the result into a corresponding word area of the second register, and a carry of the data in each word area of the second register to an upper word area using the adder; a third step of performing c times an operation of doubling by adding and writing the result into the original word area of the second register; and the binary data to be converted. c in a given order from
In a data conversion method for obtaining data in a predetermined format to be obtained in the second register by taking in data bit by bit and repeating the first to third steps, the second step and/or the third step A data conversion method characterized in that the addition operation of the adder is performed only on word areas in the second register in which there is a possibility that data will be written. 2. The data conversion method according to claim 1, wherein the predetermined format to be obtained is a BCD format. 3. Possibility of actual writing based on the data capture position when fetching c-bit data from the binary data to be converted and the write operation to the second register performed based on this fetched data. Claim 1 or 2, characterized in that the correlation between the number of word areas and the number of word areas with a certain characteristic is prepared in advance as a table, and the addition operation of the adder is controlled based on this table. data conversion method. 4. The data conversion method according to claim 3, characterized in that the table is prepared as a ROM.