JPS6219950A - Address error detection system for storage device - Google Patents

Abstract

PURPOSE:To detect completely an address-over phenomenon by setting a storage area for the differential extra storage capacity before the storage area to be allocated in case a difference is produced between the using storage capacity and the real storage capacity. CONSTITUTION:A register part 4 stores the extra storage capacity 3C produced by the difference between the using storage capacity 3B and the real storage capacity 3A of a storage part 3. An address-over detecting part 7 delivers an error signal E when an address is carried out with an address larger than the capacity 3A of the part 3. Then the position of a head address 0 which receives actual access to be allocated by the capacity 3C of the part 4 is shifted. Thus an end address N is made correspondent to the terminal of the storage area of the capacity 3A. Then an error is detected in response to access larger than the using storage area.

Description

[Detailed Description of the Invention] [Summary] Usage Note (, ”, Note 1: If there is a difference between $ffl and real storage capacity, a storage area of surplus storage capacity corresponding to the difference should be allocated.
, ff areas, it is possible to reliably detect address overflow.

[Industrial application field]

The present invention is applicable to 1. when there is a difference between the used storage capacity and the actual storage capacity. Regarding the address error detection method of a device, in particular,
The present invention relates to an address error detection method for a storage device in which a storage area whose capacity is determined by a difference in capacity is located before an area to be allocated.

Recently, a wide variety of OA equipment has been used,
The bit configuration of each device is not necessarily the same.

Therefore, in order to provide storage devices suitable for a wide variety of devices with different bit configurations, it is necessary to
Do you need to prepare storage devices of various capacities? ! ! Due to the construction, a wide variety of products are produced in small quantities, and the varnish is 1-up.

Therefore, in order to absorb differences in bit configurations depending on the equipment used, and in consideration of future interfaces, large capacity storage devices are generally used.

Therefore, since the used storage capacity is smaller than the actual storage capacity, there is an unused storage area.

Therefore, when allocating addresses, it is desired that such unused storage areas be allocated without causing any problems.

[Conventional technology]

Conventionally, the configuration was as shown in the conventional block diagram shown in FIG.

The configuration is such that a predetermined iQ area in the actual memory 1 and a capacity ff13A of the storage unit 3 is accessed via the read/write unit 2 by address designation A from the CPUI side.

Allocation of addresses to such storage areas should be turned off first.
The used storage area 3D from address 0 to the last address N is located at the front, and the unused area is written at the rear, α area 3E.
It was done so that A<M-Z.

[Problem that the invention seeks to solve]

However, with this kind of address assignment, M
If the -Z address is specified, address overflow due to the incorrect address will not be detected, and therefore it becomes possible to access the unused storage area 3E.

Therefore, due to incorrect address designation, data is stored on the third day of the α area, which is originally unused, resulting in a problem of inconsistency in the entire process.

In other words, there is a case where the address to be written and the address to be read do not match.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention.

As shown in FIG. 1, there is a register section (4) and a memory for storing surplus storage capacity (3C) due to the difference in capacity between the used storage capacity I (3B) and the actual storage capacity (3A) in the storage section (3). an address overdetection detector 1i[13(7) which outputs an error signal (E) when access is made with an address larger than the actual storage capacity value of the register section (3);
Shift the position of the first address (0) that is actually accessed to be allocated according to the surplus storage capacity (3C) in (4), and the last address (N) is the end of the storage area of the actual storage capacity (3A). , and an error is detected in response to an access beyond the α area.

With this configuration, the above-mentioned problems are solved.

[For production]

That is, when allocating storage areas, the storage area with surplus storage capacity due to the difference between the α capacity and the used storage capacity should be located before the storage area to be allocated based on the used storage capacity. This ensures that the last address is always assigned to the end of the storage area.

This makes it possible to detect address overflow and prevent troubles caused by erroneous addresses as in the prior art.

〔Example〕

The present invention will be explained in detail below with reference to FIG.

FIG. 2 is a block diagram of an embodiment according to the present invention. The same reference numerals indicate the same objects throughout the figures.

A register unit 4 is provided, which includes a setting circuit 4B that stores a surplus storage capacity 3C that is the difference between the actual storage capacity 3A and the used storage capacity 3B, and an arithmetic circuit 4A that performs calculations based on the numerical value M from the setting circuit 4B. The configuration is such that access by address 8 designated from CP LJ 1 is performed via the register section 4.

Therefore, address allocation is necessary for unused unused storage areas.1. 0 to M in the a area 3E are secured, and the usage notes to be used next are 1. The q area 3D is allocated, and the last address can be allocated to the end of the storage area.

Further, the numerical value M of the surplus storage capacity 3C stored in the setting circuit 4B needs to be configured so that it can be changed according to designation.

With this configuration, the specified address A is always accessed by adding the numerical value M, so if the memory capacity used is exceeded, the address value will naturally be greater than or equal to M + N, and a large address (, An address overflow is detected by the address overdetection section 7 of the device having one area.

Therefore, it is possible to guard 0 to M of the unused storage area 3E, and furthermore, since the last address is assigned to the end of the storage area, it is possible to easily address addresses caused by incorrect address specification without providing any extra circuitry. It becomes possible to detect overflow.

In addition, a detection unit 7 that detects such address overflow is provided.
For example, the comparison circuit 6 and the real storage capacity 3A are written as 1.
．． A comparison circuit 6 compares the address of A+M sent from the register section 4 with the actual storage capacity of 10 3 A, and detects when the address of A+M exceeds the actual storage capacity of 3 A. If address overflow is detected, the comparator circuit 6 notifies the CPU of the error signal E.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to guard against the availability of unused storage areas, and moreover, it is possible to detect address overs, which have not been detected conventionally.

Further, even if the storage capacity used changes due to a change in the equipment or interface used, addresses can be easily allocated, which has a great practical effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the present invention. FIG. 2 is a block diagram of an embodiment according to the present invention. FIG. 3 shows a conventional block diagram. In the figure, ■ is the CPU, and 2 is the read/write section. 3 is a storage section, and 4 is a register section. 7P-f The Source of Sun and Moon 5 A Flopaba Illustrated Spear 1 Fronf Prisoner of Fronfu Rozuki (=Jro Ichiro Shichisushi) 2
Bron 2 of Ku Hyo 3 Figure

Claims (1)

[Scope of Claims] A memory that assigns addresses to a predetermined storage area of the storage unit (3) so that the predetermined storage area of the storage unit (3) can be accessed via the read/write unit (2) by specifying a predetermined address (A). An address error detection method of a device, which detects surplus storage capacity (3C) due to the difference in capacity between the used storage capacity (3B) and the actual storage capacity (3A) in the storage unit (3).
) and the storage unit (3)
an address overdetection section (7) that outputs an error signal E when accessed with an address larger than the actual storage capacity value of the register section (4);
3C), shift the position of the first address (0) to be allocated and actually accessed so that the last address (N) corresponds to the end of the storage area of the actual storage capacity (3A), and reduce the used storage area. An address error detection method for a storage device, characterized in that an error is detected for an access that exceeds the limit.