JPH04353946A - Confirming method for memory storage capacity - Google Patents

Abstract

PURPOSE:To automatically confirm the setting address and the storage capacity of an extension memory space at high speed without the need of work for setting the start address and the storage capacity of the extension memory space. CONSTITUTION:At first, the prescribed address of the memory space 21 is accessed and the address is compared and checked. Then, access is executed by enlarging a setting period in the memory space 21 in one direction until the presence or absence of the occurrence of the error is switched. When the presence or absence of the occurrence of the error is switched, the access direction of the address is switched in an opposite direction, the setting period is reduced and access is executed. When an operation is repeated and the start address and the end address are detected, the setting address and the storage capacity of an extension memory space 22 can be confirmed based on the both addresses.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for checking memory storage capacity when expanding memory.

0002

[Prior Art] Conventionally, when the memory storage capacity of various devices is insufficient, it has been possible to expand the memory. It has become. FIG. 2 is an explanatory diagram of a conventional method for checking memory storage capacity.

In the figure, 1 is a memory space, 2,
3 is an expansion memory chip, 2a has a start address of AH
, an additional memory space with a storage capacity of X, and 3a is an additional memory space with a start address of BH and a storage capacity of X'. 4 and 5 are switches for setting the start addresses AH and BH in the expansion memory chips 2 and 3, and 6 and 7 are switches for setting the storage capacities X and X' in the expansion memory chips 2 and 3. .

These switches 4 to 7 are configured to be set individually according to the requirements of a system (not shown), and a microprocessor (not shown) adjusts the settings of the switches 6, 7 of the expansion memory chips 2, 3. The data corresponding to the contents is read and it is recognized whether the memory chip 2 is an expansion memory chip 2 with a storage capacity of X or an expansion memory chip 3 with a storage capacity X'.

In the case of another confirmation method, a compare check is performed by accessing each address of the additional memory spaces 2a and 3a obtained by mounting the additional memory chips 2 and 3, and writing and reading specific data. The switching point between normal and abnormal results of the compare check is detected, and whether or not the expansion memory chips 2 and 3 are installed, the set addresses and storage capacities X and X' of the expansion memory spaces 2a and 3a are determined. It is supposed to be confirmed.

[0006]

However, in the conventional memory storage capacity confirmation method described above, the switches 4 and 5 for setting the start addresses AH and BH in the expansion memory chips 2 and 3 and the storage capacities X and X' In the case of the method of providing switches 6 and 7 for setting the memory chips, it is necessary to set the switches 4 to 7 before adding memory chips, which is complicated and may lead to setting errors. be.

[0007] Furthermore, the processor has an additional memory chip 2,
3, by comparing and checking the additional memory spaces 2a, 3a, it is possible to check whether or not the additional memory chips 2, 3 are mounted, and the set address and storage capacity X, X' of the additional memory spaces 2a, 3a. In this case, if the additional memory spaces 2a and 3a are large, it takes too much time to perform the compare check.

[0008] The present invention solves the problems of the conventional memory storage capacity confirmation method described above, and allows setting of an additional memory space without requiring work for setting the start address of the additional memory space or setting the storage capacity. An object of the present invention is to provide a memory storage capacity confirmation method that can automatically and quickly recognize an address and storage capacity.

[0009]

[Means for Solving the Problems] To this end, in the memory storage capacity confirmation method of the present invention, when allocating an additional memory space composed of RAM to the system memory space, first, a predetermined address of the memory space is accessed. Data is written, read and compared to that address, and it is determined whether an error has occurred.

[0010] The address of the memory space is changed from the low address side to the high address side until the occurrence of an error is switched.
Alternatively, access is performed at a set cycle that gradually increases in one direction from the high address side to the low address side. Each time the presence or absence of an error is switched, a compare check is performed on the previous address, and at this time, the start address or end address of the additional memory space is detected by switching again between the presence and absence of an error. Ru.

[0011] If the start address or end address is not detected, access is performed in the opposite direction at a set cycle that gradually becomes smaller. The set cycle for accessing the memory space is based on the number of bits of a memory chip with the smallest storage capacity among the memory chips used in the system, or is set to the power of 2 M (an integer).

0012

[Operation] According to the present invention, when an additional memory space consisting of RAM is allocated to the system memory space as described above, a predetermined address in the memory space is first accessed, and data is stored at that address. Writing, reading, and compare checking are performed to determine whether an error has occurred.

[0013] Until the occurrence of an error is switched, the address of the memory space is changed from the low address side to the high address side.
Alternatively, access is performed at a set cycle that gradually increases in one direction from the high address side to the low address side. When the presence or absence of an error is switched, a compare check is performed on the previous address, and at this time, the presence or absence of an error is switched again, thereby detecting the start address or end address of the additional memory space. .

[0014] If the start address or end address is not detected, the direction of address access is switched to the opposite direction, and access is performed at a set cycle that gradually becomes smaller. Then, when the presence or absence of an error is switched, a compare check is performed on the previous address, and if the start address or end address is not detected, the direction of address access is switched again, and the access direction is changed again. The setting cycle of is made smaller.

When the above operation is repeated and the start address and end address are detected, the set address and storage capacity of the additional memory space can be confirmed based on both addresses. The set cycle for accessing the memory space is based on the number of bits of a memory chip with the smallest storage capacity among the memory chips used in the system, or is set to the power of 2 M (an integer).

[0016]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is an explanatory diagram of the memory storage capacity confirmation method of the present invention, FIG. 3 is a first flowchart of the operation of detecting the start address of the additional memory space, and FIG. 4 is a second flowchart of the operation of detecting the start address of the additional memory space. , FIG. 5 is a first flowchart of the operation for detecting the end address of the additional memory space, and FIG. 6 is a second flowchart of the operation for detecting the end address of the additional memory space.

In FIG. 1, 21 is a memory space, and 22 is an additional memory space that is added to a predetermined position of the memory space 21. In FIG. Based on FIGS. 3 and 4, the memory space 21 is accessed at a set period, and depending on whether an error occurs,
A method for detecting the start address of the additional memory space 22 will be explained. Step S1: Store a predetermined memory address value (for example, 2 to the Nth power) in an AC register (register that specifies the current address). Step S2 Writes and reads specific data to and from the specified address stored in the AC register,
Perform a compare check. Steps S3 and S4: Determine whether or not the result of the compare check is an error. If there is no additional memory space 22, an error will occur, and the contents of the above AC register will be stored in the AOL register (a register that stores the old address on the low address side), and the setting period will be set to the M power of 2 to access again. The contents of the AC register are doubled and stored in the AC register again. At this time, the access setting cycle is 2 to the N power (M
=N). Then, a compare check is performed again on the newly specified address. In this case, the address is 2
Since the address is raised to the (N+1) power, an error occurs in the same manner as the address of 2 to the N+th power, and the compare check is normally performed when the address becomes 2 to the (N+2) power. The set cycle at this time is 2 to the (N+1) power (M=N+1)
.

Note that the reason why the contents of the AC register are doubled in step S4 is to access from the low address side to the high address direction, and when accessing from the high address side to the low address direction, the AC register contents are doubled. The contents of 1
/ Multiply by 2. Step S5 When the compare check is successfully performed, in order to check whether it is the start address of the expansion memory space 22, check the address (AC-1 address) immediately before the address specified by the AC register.
A similar compare check is performed on . Step S
6 Determine whether the result of the compare check is an error. If an error occurs, the process advances to step S23, where the start address of the additional memory space 22 is detected based on the contents of the AC register. Step S7 If no error occurs in the compare check, store the contents of the AC register (in this case, 2 to the power of (N+2)) in the AOH register (register that stores the old address on the high address side), and store the contents of the AOL register. remains the previous value and sets 2 to the (N+1) power, and A
A new value intermediate between the value of the AOH register and the value of the AOL register is set in the C register. The setting cycle at this time is
It is 2 to the N power (M=N). Step S8 Address set in the AC register (in this case, 2(N+1)
2 to the Nth power)). Steps S9 and S10: Determine whether or not the result of the compare check is an error. If there is no additional memory space 22,
Since the compare check results in an error, the contents of the AC register are stored in the AOL register, the contents of the AOH register are set to the power of 2 (N+2) with the previous value, and the value of the AOH register and the value of the AOL register are stored in the AC register. Set a new intermediate value. Steps S11 to S14 Perform a compare check on the new address specified by the AC register, repeat this until it completes normally, and if it completes normally, check the address immediately before the address specified by the AC register (AC -1 address). If an error occurs, the process advances to step S23, and the value of the AC register becomes the start address of the additional memory space 22. If no error occurs, step S7
Return to , and repeat the operations described above. Step S15
If no error occurs in step S9, A
A compare check is performed on the address (AC-1 address) immediately before the address specified by the C register. In the case of this embodiment, no error occurs in the compare check in step S8 because the additional memory space 22 exists at the address specified by the AC register. Step S16: It is determined whether the result of the compare check is an error. If an error occurs, the process advances to step S23 and the start address is detected. Steps S17, S18
If no error occurs, the contents of the AC register (in this case, 2 to the power of (N+1) + 2 to the power of N) are stored in the AOH register, and the contents of the AOL register remain as the previous value.
N+1) power, set a new value in the AC register between the value of the AOH register and the value of the AOL register, and
The address set in the register (in this case, 2 (N+
1) A compare check is performed on the (N-1) power of +2 to the (N-1) power). The set cycle at this time is 2 to the (N-1) power (M=N-1). Steps S19 to S23 If there is no additional memory space 22, the result of the compare check will be an error, so the contents of the AC register are stored in the AOL register, and the contents of the AOH register remain as the previous value (2).
N + 1) power + 2 to the N power, set a new value in the AC register between the value of the AOH register and the value of the AOL register, perform a compare check on the new address specified by the AC register, and complete normally. Repeat until. If the process ends normally, proceed to step S1 in the same way as described above.
Returning to step 5, a compare check is performed on the address (AC-1 address) immediately before the address specified by the AC register. In the case of this embodiment, no error occurs in the compare check in step S18 because the additional memory space 22 exists at the address specified by the AC register. Then, repeat the above operation (step S
15, S16, S17, S18, S19, S15, S1
6,...), the start address of the additional memory space 22 is 2 to the power of (N+1) + 2 to the power of (N-1) + 2 to the power of (N-
3) Detect the power. The setting cycle at this time is 2 (N-3
) power (M=N-3).

Next, the operation of detecting the end address of the additional memory space 22 will be explained based on FIGS. 5 and 6. Steps S30, S31 A predetermined memory address value (a specific address in the additional memory space 22, for example 2
(N1 power)) is stored in the AC register, specific data is written to and read from the address specified in the AC register, and a compare check is performed. Step S3
2, S33 Determine whether or not the result of the compare check is an error. In this embodiment, since there is an additional memory space 22 at the address specified by the AC register, no error occurs, and the contents of the AC register are stored in the AOL register, and the contents of the AC register are doubled.
The data is stored in the AC register again, and a compare check is performed on the newly designated address. Step S
34 Repeat the above operations in sequence until a compare check error occurs (in this embodiment, until the address of the AC register becomes 2 to the (N+3) power). When an error occurs, a compare check is performed on the address immediately before the address specified by the AC register (AC-1 address) to check whether it is the end address of the additional memory space 22. conduct. Steps S35 to S37
Determine whether or not the result of the compare check is an error. In this example, an error still occurs at this point, so
The contents of the AC register (in this case, 2 to the power of (N+3)) are stored in the AOH register, the contents of the AOL register are kept as 2 to the power of N1, and A is stored in the AC register.
A new value between the value of the OH register and the value of the AOL register is set, and a compare check is performed on the address set in the AC register. It is determined whether or not the result of the compare check in steps S38 and S39 is an error. If an error occurs, a compare check is performed on the address immediately before the address specified by the AC register (AC-1 address) in order to confirm whether it is the end address of the additional memory space 22. Step S40: Determine whether or not the result of the compare check is an error. If it is not the end address of the additional memory space 22, an error occurs and steps S36, S37, S38, S39,
The operation in S40 is repeated, and when no error occurs in step S38 (when the additional memory space 22 is accessed), the process advances to step S41. Steps S41-S
43 Store the contents of the AC register in the AOL register, and keep the contents of the AOH register as 2 (N+3).
and the AC register contains the value of the AOH register and AOL
A new intermediate value between the register values is set, a compare check is performed on the new address specified by the AC register, and the process is repeated until an error occurs. Step S44
When an error occurs, a compare check is performed on the address (AC-1 address) immediately before the address specified by the AC register. Step S45: It is determined whether the result of the compare check is an error. If an error occurs, the process returns to step S36, repeats the above operations, and detects 2 to the (N+2) power + 2 to the N power + 2 to the (N-3) power - 1 as the end address of the additional memory space 22.

In this way, the start address, end address, and storage capacity of the additional memory space 22 can be automatically detected without accessing the entire area of the memory space 21 and with a small number of accesses. This is particularly effective when the memory space 21 of the system is large or when handling various types of additional memory chips. In addition, in this embodiment, a method that can be detected even when the start address, end address, and storage capacity of the expansion memory space 22 are set to arbitrary values has been explained. However, if the start address, end address, and storage capacity of the expansion memory space 22 are For example, in the case of an embodiment in which the number of bits is an integral multiple of 64K bits, the compare check may be performed at a cycle of 64K bits.

In particular, the memory chip is 64K bits, 1
Since the memory capacity increases by doubling or quadrupling the size to 28K bits, 256K bits, 1M bits, 4M bits, etc., the memory chips used in the additional memory space 22 allocated to the memory space 21 of the system are It is preferable to set the compare check period to the bit number of the smallest memory chip.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0023]

As described in detail above, according to the present invention, an address in a memory space is accessed, a compare check is performed on the address, and it is determined whether an error has occurred. Then, access is performed at a set cycle that gradually increases in one direction until the presence or absence of an error is switched, and each time the presence or absence of an error is switched, the start address or end address of the additional memory space is checked. If the start address or end address is not detected, the direction of access is switched to the opposite direction, and access is performed at a set cycle that gradually becomes smaller.

[0024] Therefore, the start address and end address of the extended memory space can be automatically detected with a small number of accesses, and the position and storage capacity of the extended memory space in the system memory space can be confirmed. . In addition, the storage capacity of a memory chip (expansion memory space) can be expressed as 2 to the power of M (an integer), and for example, 64K bits, 128K bits, 2
56K bits, 1M bits, 4M bits, etc. and double or 4
Since the storage capacity increases by doubling the size, the start address, end address, and storage capacity of the expanded memory space are integral multiples of the memory chip with the smallest storage capacity among the memory chips used. Therefore, if the setting cycle for accessing the memory space is set to the number of bits of the memory chip with the smallest storage capacity among the memory chips used in the above system, or to the power of 2 M (an integer), then the additional memory The number of accesses required to detect the start address and end address of the space can be reduced.

In particular, even when dealing with multiple types of additional memory chips with different storage capacities, the storage capacity can be easily checked.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a memory storage capacity confirmation method according to the present invention.

FIG. 2 is an explanatory diagram of a conventional memory storage capacity confirmation method.

FIG. 3 is a first flowchart of an operation for detecting a start address of an additional memory space.

FIG. 4 is a second flowchart of an operation for detecting a start address of an additional memory space.

FIG. 5 is a first flowchart of an operation for detecting an end address of an additional memory space.

FIG. 6 is a second flowchart of an operation for detecting an end address of an additional memory space.

[Explanation of symbols]

21 Memory space 22 Expansion memory space

Claims (3)

[Claims] Claim 1. In a method for checking memory storage capacity when allocating an additional memory space consisting of RAM to a system memory space, (a) an address in the memory space is accessed; (b) for the accessed address, Write, read, and compare check data, (c
) As a result of the compare check, it is determined whether or not an error has occurred, and (d) until it is switched whether an error has occurred or not,
Addresses in the memory space are accessed in one direction at a set cycle that gradually increases, and (e) each time the presence or absence of an error changes, a compare check is performed on the previous address to start/start the expanded memory space. A method for checking memory storage capacity, comprising: detecting an end address; and (f) accessing in the opposite direction at a set cycle that gradually becomes smaller when the start/end address is not detected. 2. The memory storage capacity according to claim 1, wherein the set cycle for accessing the memory space is based on the number of bits of a memory chip with the smallest storage capacity among the memory chips used in the system. Confirmation method. 3. The method for checking memory storage capacity according to claim 1, wherein the set period for accessing the memory space is 2 to the power of M (an integer).