JPH08235894A - Flash memory and flash memory control device - Google Patents

Abstract

PURPOSE: To make the overhead reaching respective operations of an erasing, a writing and a read-in and the variation of access times for every chip small by providing areas where position management information of areas where users are accessible and areas where users are not accessible are stored with prescribed formats in a flash memory. CONSTITUTION: A flash memory 100 is divided into n storage areas 101 to 10n and it an access to the memory 100, an erasing, a writing and a read-in are executed by making each area as one boundary. Position management information of areas where users in the same chip are accessible and areas where users are not accessible area stored with prescribed formats respectively in first and second areas and the third and the fourth areas and succeeding areas 103 to 106 are data storage areas where users can access freely. Thus, since the inspecting of storage areas as a pre-processing performing an access is made unnecessary, the overhead reaching respective operations is made small and the variation for every memory chip is made small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory capable of erasing a storage area of a predetermined range at a time,
In particular, it relates to presentation of defect information of a flash memory at the time of production and a flash memory control device using such a flash memory.

[0002]

2. Description of the Related Art Since a flash memory has an advantage that stored contents are retained even when the power is turned off, there is an increasing demand for it to be used as an external storage device for game machines and OA equipment. However, in the current manufacturing technology, there is a predetermined limit on the number of times of erasing and writing of the flash memory, and the storage area portion exceeding the limit cannot be used thereafter. Further, some of them already have several defective areas at the time of manufacturing and shipping.

Examples of conventional techniques for compensating for these drawbacks are disclosed in Japanese Patent Laid-Open Nos. 6-28899 and 6-36579, in which the storage area of a flash memory is divided into predetermined areas in advance, and An example is shown in which the position of the storage area that exceeds a predetermined number of times is detected as a defective area by counting the number of times of erasing and writing to the storage area.

Further, in Japanese Laid-Open Patent Publication No. 6-12596, when a flash memory is accessed, a predetermined storage area or all storage areas are written and / or read, or both are stored. An example is shown where a test is being performed to see if the area is normal.

Further, in Japanese Unexamined Patent Publication No. 6-131892, the flash memory itself has an area in which location management information of a defective area is written in advance, and a user reads the location management information to determine an access area of the flash memory. An example of doing so is shown.

[0006]

In the methods disclosed in JP-A-6-28899, JP-A-6-36579, and JP-A-6-12596, the pre-processing for accessing an arbitrary storage area of the flash memory is always required. It is necessary to check whether or not the storage area is an accessible area, and there is a problem that the overhead until the actual writing and reading operations is large. Further, in addition to the flash memory, it is necessary to prepare a volatile memory or the like for storing the location management information of the defective area, and the number of parts constituting the apparatus increases.

Further, in the method according to the above-mentioned Japanese Patent Laid-Open No. 6-131892, the flash memory itself has an area in which the position management information of the defective area has been written in advance, and the volatile memory for storing the position management information of the defective area is provided outside. It is not necessary to provide a memory for memory. However, as in the prior art, even if the storage area to be accessed from now on is a usable storage area, it is determined whether all the above-mentioned location management information of the inaccessible area and the defective area are defective. The above comparison must be performed, and the more defective areas of the flash memory, the greater the overhead until data reading. Further, since the number of defective areas for each chip of the flash memory is not always a fixed number, there is a problem that the access time varies for each chip.

[0008]

In order to solve the above problems, the present invention accesses a predetermined portion of the flash memory in a predetermined format at the time of manufacturing the flash memory or at the latest before the flash memory reaches a user. And an area in which location management information of an accessible area in a predetermined format is stored in a predetermined storage area of the flash memory.

Further, in the control device using the flash memory, when a defective storage area is generated during the use of the flash memory, an arbitrary memory is used to prohibit the use of the storage area thereafter. When a defect diagnosis of the storage area is performed after the area is accessed and a defect is detected, the area number of the storage area is stored in the area in which the position management information of the inaccessible area is stored, and the accessible area. And a control means for updating the information of the area storing the position management information.

[0010]

According to the present invention, the location management information of the inaccessible area and the location management information of the accessible area are stored in the predetermined area of the flash memory. It is not always necessary to check whether or not the storage area is an accessible area as a pre-process for accessing. The area number of the storage area to be accessed from now on only needs to be read from the part that stores the position management information of the accessible area,
It is possible to reduce the overhead of each operation of erasing, writing, and reading, and to reduce the variation in access time that has conventionally occurred for each chip of the flash memory.

Furthermore, even if defective storage areas are scattered in the flash memory, they can be treated as a continuous memory space in appearance.

Furthermore, it is possible to omit a volatile memory or the like for storing position management information of an inaccessible area or an accessible area other than the flash memory, and the number of parts of the device using the flash memory can be omitted. Can be configured less.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The example shown in FIG. 1 is a block diagram showing the state of a storage area in a flash memory according to an embodiment of the present invention. The flash memory 100 is divided into n storage areas 10l to 10m in advance, and access to the flash memory 100 is performed by erasing, writing, reading, etc. with each storage area as one boundary. In the first storage area 101, position management information of a storage area inaccessible to a user in the same chip is stored in a predetermined format described later. In the second storage area 102,
Position management information of a storage area accessible by the user in the same chip is stored in a predetermined format described later.
The first storage area and the second storage area are prepared in a predetermined format in a predetermined portion of the flash memory at the time of manufacturing the flash memory or at the latest by the time the flash memory reaches the user. Is.

The third and subsequent storage areas 103 to 106 are data storage areas which the user can freely access. However, depending on the chip of the flash memory, the positions of the first storage area 101 and the second storage area 102 may be defective storage areas. In such a case, the data may be shifted and stored in the third storage area 103 and the fourth storage area 104, respectively. Although not shown, at this time, as a means for allowing the user to recognize that the location management information is moved and stored, an identification code for distinguishing it from the data storage area is stored at the beginning of the storage area. You may stay.

The example shown in FIG. 2 is an embodiment showing the format of the storage area 101 of the flash memory. The storage area 101 stores location management information of a storage area in which the user cannot access the flash memory.

Here, as an example, the storage area 101 has addresses 000 (200) to FFF (20n).
Of the flash memory and has sufficient capacity to store the numbers of all storage areas of the flash memory. At the address 000 (200), the memory ID for the user to distinguish from the management information of other flash memories
To store. However, it can be omitted when only one flash memory is used and the memory ID is not particularly required. At address 001 (201),
The total number of defective storage areas existing in the flash memory is stored, and the area number of the defective storage area is stored after address 002 (202).

For example, when the content of the address 001 (201) is 001, it indicates that there is one defective storage area in the flash memory, and the area number of the storage area is stored in the address 002 (202). It In the example of the figure,
This shows that the 003rd storage area of the flash memory is a defective storage area. Although not shown, for example,
If the content of the address 001 (201) is 003, it means that there are three defective storage areas in the flash memory, and the address 002 (202), the address 003.
The area numbers of defective storage areas are stored in (203) and address 004 (204), respectively. If the content of the address 001 (201) is 0, it means that there is no defective storage area in the flash memory.
Data after 02 (202) is meaningless.

The example shown in FIG. 3 is an embodiment showing the format of the storage area 102 of the flash memory shown in FIG. The storage area 102 stores location management information of a storage area accessible by the user in the flash memory. Like the storage area 101, the storage area has a memory from address 000 (300) to address FFF (30n), and has a sufficient capacity to store the numbers of all the storage areas of the flash memory. To do. The address 000 (300) stores the total number of accessible areas in the flash memory, and the address 001 (30
After 1), the area numbers of accessible storage areas are stored in ascending order. However, the total number of accessible areas is obtained by subtracting the total number of defective storage areas in the first storage area (101 in FIG. 1) from the total number of storage areas. It may be omitted.

The example shown in the figure shows a case where the total number of accessible areas is hexadecimal F00 and one of the defective storage areas is an area number 003. Therefore, the address 0
Area numbers 001, 0 in the memory after 01 (301)
It is stored in the order of 02,004,005.
By these means, even if defective areas are scattered in the flash memory, the user can use them as a continuous memory space without paying particular attention to the positions of the defective areas. When the content of the address 001 (301) is 000, it means that there is no accessible storage area in the flash memory, which means that the flash memory cannot be used at all.

Although not shown, the address 001 (30
The arrangement of the area numbers stored after 1) may be in the descending order of the area numbers or another predetermined order depending on the use, and the order is not particularly limited.

The example shown in FIG. 4 is a flow chart showing an embodiment of a procedure for accessing the flash memory while referring to the position management information of the accessible storage area. First, the number of storage areas of the flash memory corresponding to the memory capacity required for access is Bn (401), and the chip number of the flash memory to be accessed from now on is A.
cn (402). Next, the total number of accessible storage areas is read from the address 000 of the second storage area of the chip number Acn, and this is set as Tn (403). If the number of accessible storage areas Tn is 0 (40
4) The error process (416) described later is executed. Tn is 0
If not, one area number Tbn of the accessible storage area is read from the second storage area of the chip number Acn.
(405), the storage area Tbn of the chip number Acn is accessed (406).

Next, it is judged whether or not the accessed storage area is an inaccessible defective storage area that has reached the limit of use by means such as counting the number of erases of each storage area (407). . If the storage area Tbn is determined to be a defective storage area, the chip number A
The area number Tbn is added to the first storage area of cn (41
2), +1 is added to the total number of defective storage areas in the first storage area (413). Further, the area number Tbn is deleted from the second storage area of the same chip (414), and -1 is added to the total number of accessible storage areas of the second storage area (41).
5). Although not shown, the area numbers Tbn may be deleted from the second storage area to rearrange the area numbers so that the information does not become discontinuous information.

After that, the number of accessible storage areas Tn is updated and the processing is restarted. If the storage area Tbn is not a defective storage area, Tn is added by -1 (408). If the storage area of the chip number Acn becomes FULL (Tn = 0), error processing (416) described later is performed. If it is not FULL yet, -1 is added to the number Bn of storage areas required for access (410). If all the accesses have not been completed (Bn ≠ 0), one area number Tbn of the accessible storage area is further read from the second storage area of the chip number Acn, and the processing is continued. If all accesses are completed (Bn = 0), this process is completed.

Here, an example of the error processing (416) will be described. For example, when there is a usable flash memory other than the flash memory, the chip number to be accessed may be reset to another chip number and the processing may be restarted. If there is no other available flash memory, the process up to this point may be interrupted, and the user may be warned by externally displaying that a memory access failure has occurred.

The example shown in FIG. 5 is an embodiment of the configuration of the flash memory control device according to the present invention. The flash memories 503 to 506 are preliminarily divided into n storage areas, and access to the memory is performed for each storage area. The input / output unit 507 is a unit that inputs and outputs data and various control information between the device of this embodiment and a device connected to the outside. Defect detection unit 502
Is a part that counts the number of erases and writes to each storage area of the flash memories 503 to 506, and determines whether or not the storage areas of the flash memories 503 to 506 have reached the limit of use and are defective storage areas. This is the part that is referred to when doing. The RAM 501 is a portion for temporarily storing the area numbers of all defective storage areas scattered in the flash memories 503 to 506 or the area numbers of usable storage areas for each chip.

As described above, the area number of the storage area to be accessed may be read directly from the flash memory, but an external RAM 501 is provided in consideration of the management information update processing when a defective storage area occurs. The management information may be temporarily saved in the RAM 501 and accessed here. Further, even when the defect detection unit 502 detects an unusable storage area while using the flash memory, the area number of the storage area is RAM5.
01 is additionally stored. Note that the management information is temporarily RA
In the case of saving to the M501, a process of saving the management information of the RAM 501 in the first storage area or the second storage area of the flash memory is required immediately before all the processing is finished and the power of the apparatus is stopped. The control unit 500 is a unit that performs writing, reading, and erasing on the flash memories 503 to 506, and a unit that controls input / output of information to / from the defect detection unit 502 and the RAM 501.

The number of flash memories 503 to 506 prepared in this embodiment is arbitrary, and the number is not particularly specified.

[0028]

According to the present invention, position management information of an area in which a predetermined area of a flash memory cannot be accessed,
Further, by storing the position management information of the accessible area, it is not necessary to inspect whether or not the storage area is accessible as a pre-process for accessing an arbitrary storage area of the flash memory. The area number of the storage area to be accessed from now on only needs to be read from the portion in which the position management information of the accessible area is stored, and the overhead of the erase, write, and read operations is reduced. In addition, it is possible to reduce the variation in access time that has conventionally occurred for each chip of the flash memory.

Furthermore, even if defective storage areas are scattered in the flash memory, they can be treated as a continuous memory space in appearance.

Further, it is possible to omit a volatile memory or the like for storing the position management information of an inaccessible area or an accessible area other than the flash memory, and the number of parts of the apparatus using the flash memory can be omitted. Can be configured less.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a state of a flash memory of the present invention.

FIG. 2 is an explanatory diagram showing a format of a first storage area in FIG.

3 is an explanatory diagram showing a format of a second storage area in FIG. 1. FIG.

FIG. 4 is a flowchart showing an example of a procedure for accessing a flash memory.

FIG. 5 is a block diagram of an embodiment of a flash memory control device of the present invention.

[Explanation of symbols]

100 ... Flash memory, 101, 102 ... Storage area, 500 ... Control unit, 501 ... RAM, 502 ... Defect detection unit, 503 to 506 ... Flash memory, 507 ... Input / output unit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takeshi Tottori 1-88-1 Tora, Ibaraki City, Osaka Prefecture Hitachi Maxell Co., Ltd.

Claims (2)

[Claims] 1. A predetermined storage area of a flash memory has an area storing location management information of an inaccessible area in a predetermined format, and a predetermined storage area of the flash memory can be accessed in a predetermined format. A flash memory having an area in which position management information of possible areas is stored. 2. A means for reading position information of a defective area of the flash memory from an area storing position management information of one or a plurality of defective areas of the flash memory, and a position of the defective area. Means for writing information, means for reading the position information of the usable area of the flash memory from the area storing position management information of the usable area of the flash memory, and means for rewriting the position information of the usable area, A means for inputting / outputting data to / from the outside and a means for controlling these means are provided, and even if there is a defective area in the flash memory, it is possible to judge whether the area to be accessed is an available area or not. Optional flash memory controller.