JP2004252746A - Recording control method and device for recording medium, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the speed of writing processing speed for a recording area where data with predetermined contents are written in the predetermined order of addresses, as in TOC areas, on a recording medium, such as a flash memory. <P>SOLUTION: The proper address position in a predetermined memory area where each group of data should be written is converted into a converted address position where data are arranged in the order of addresses in the memory area, in response to writing instructions for each group of data, whereby each group of data is written in sequence in the predetermined memory area. Information showing the correspondence between the proper address position and the converted address position is retained for reading each group of data. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a recording control method and apparatus suitable for writing control of a recording medium such as a flash memory, in particular, a TOC (Table of Contents) area.
[0002]
[Prior art]
The configuration of the recording data handled by the NAND flash memory is, for example, as shown in FIG. 14. Data is read and written in small block units called pages, and large data called blocks formed of a plurality of pages. Data is erased in block units.
[0003]
One page includes, for example, a 512-byte data area and a 16-byte spare area (redundant portion). Four bytes of the 16-byte spare area are used as an ECC (Error Correction Code) for error detection and correction.
[0004]
The method of controlling the reading and writing of the flash memory is, for example, as described in Japanese Patent Application Laid-Open No. 2000-31104.
[0005]
The recording control device that controls reading and writing of the flash memory manages, at a block unit, at which physical address of the flash memory data has been written by using a logical address. And a logical-physical address conversion table for performing conversion between physical addresses and logical addresses of the flash memory. The recording control device performs address control of the flash memory using the logical-physical address conversion table.
[0006]
In this case, the logical address is written in the spare area of each page. The spare area includes an updating flag indicating whether or not the logical address is being written to the block. The updating flag is turned on ("0") when writing is being performed, and is off ("1") when writing is not being performed.
[0007]
Next, an operation of writing data in page units in the NAND flash memory will be described. In this case, in the NAND flash memory, the write target block and the write target page can be determined at random. However, in the write processing procedure in the same block, from the top page of the address number, according to the address order. There is a restriction that it must be done. That is, in the same block, it is necessary to write data in order from the page with the smallest address. For this reason, conventionally, even in the case of writing in page units, the writing operation is performed in block units including the write target page.
[0008]
FIG. 15 is a diagram for explaining the outline of the page data write operation.
[0009]
That is, when writing page data to an empty area of one page in a certain block, an empty area of one block is prepared, and new data is written to a write target page address of the empty area. The data on the other pages of the block is copied from the original data. Then, after the writing process is completed, the original block is erased.
[0010]
FIG. 16 is a flowchart of the processing operation at the time of data writing, and mainly describes the processing executed by the recording control device that controls the reading and writing of the flash memory described above.
[0011]
That is, the recording control device determines whether or not a write instruction to the flash memory has been issued (step S1), and if it is determined that the write instruction has not been issued, performs other processing (step S2).
[0012]
When it is determined in step S1 that a write instruction has been issued, the recording control device determines the logical addresses of the write target block and the write target page (step S3), and updates the first page of the block of the logical address. The middle flag is turned on (step S4).
[0013]
Next, logically, a free block area in which a write target block is saved in a spare free area prepared in the logical physical address conversion table of the recording control device and a block having the same logical address as the logical address of the write target block can be written. (Step S5). The processing in step S5 will be further described with reference to FIG.
[0014]
That is, for example, as shown in FIG. 17, the flash memory has the effective area from the logical block address A to the logical block address A + n−1, and has a spare area for one block of the logical block address A + n. . Here, it is assumed that the spare area of the logical block address A + n has been erased and is an empty area.
[0015]
In the example of FIG. 17, it is assumed that the write target block is a block of the logical block address A + 3. Thus, in this example, in step S4, the updating flag of the spare area in the first page of the block of the logical block address A + 3 is turned on as shown in FIG.
[0016]
In step S5, the recording control device changes the logical block address of the logical block address A + 3, which is the write target block, to the logical block address A + n of the spare area on the logical physical address conversion table. At this time, the logical address of the spare area on the block data of the logical block address A + 3 is not rewritten.
[0017]
The logical block address of the spare area whose logical block address was A + n is converted to A + 3 on the logical / physical address conversion table. The replacement of the logical address is performed so that A + 3 is written in the logical address of the spare area of the block to be newly written.
[0018]
Then, by the replacement of the logical addresses, logically, the original block data to be written is evacuated to the spare area, and the logical block address where the original block data to be written becomes an empty area. Become.
[0019]
When the processing in step S5 as described above is completed, the recording control device writes all the page data in the address order preceding the page to be written, as indicated by (1) -1 in FIG. The target original block is copied to the corresponding page of the write destination block area (step S6). However, at this time, the updating flag of the spare area of the first page of the copy destination block is turned off.
[0020]
Next, as shown by (1) -2 in FIG. 15, the recording control device writes the data of the write target page to the corresponding page of the write destination block area (step S7).
[0021]
Next, as shown by (1) -3 in FIG. 15, the recording control device transfers all the page data of the address order after the page to be written from the original block to be written to the block area of the write destination. (Step S8).
[0022]
As described above, when rewriting of data of all pages of the original block to be written is completed, the recording control device logically replaces the data of the original block to be written, which has been evacuated to the spare area. Erase (step S9). As a result, the logical spare area becomes an empty area.
[0023]
Next, the recording control device determines whether or not the writing has been completed (step S10), and if not, returns to step S3 to determine the next block to be written and the next page to be written. repeat. When it is determined in step S10 that the writing has been completed, the writing processing routine is ended.
[0024]
By the way, if the power supply voltage is cut off during the above-described writing process due to a power failure or running out of battery, the writing process will not be completed. Conventionally, in order to cope with such a case, reset processing is performed when the power supply voltage is turned on again, so that no problem occurs in address management of the flash memory.
[0025]
FIG. 18 is a flowchart illustrating a reset process when the power supply voltage is turned on again.
[0026]
That is, when the power supply voltage is turned on again, the recording control device starts the reset processing of FIG. 18, searches the logical address of the spare area of the first page of each block, and finds two blocks having the same logical address. It is determined whether or not there is (step S21).
[0027]
As described above, since the logical address of the spare area on the page data of the original block to be rewritten evacuated to the spare area is logically the same as the original, the spare area on the page data of the block of the rewrite destination remains It is in the same state as the logical address. Therefore, when the power is turned off during the writing process, there are two blocks having the same logical address. However, since the updating flag is turned on in the original block to be rewritten, it can be distinguished from the rewriting destination block in which the updating flag is off.
[0028]
Based on the above, when it is determined in step S21 that there are two blocks having the same logical address, it is determined that the power supply has been interrupted during the write process, and the updating flag of the two blocks is determined. Are left on, and all the data of the blocks for which the updating flag is off are erased (step S22). This returns to the state before the page write processing. Then, the reset process ends, and the process proceeds to the next process.
[0029]
When it is determined in step S21 that there is only one block having the same logical address, it is determined that there is no write process in progress, the reset process is terminated, and the process proceeds to the next process.
[0030]
[Patent Document 1]
JP 2000-311104 A
[0031]
[Problems to be solved by the invention]
As described above, in the conventional flash memory recording control method, every time one page of data is written, all the pages of one block are rewritten (including the copy) to the write destination block, and the source of the write target is written. Block is erased.
[0032]
Therefore, the writing of one page of data involves writing and erasing in units of blocks, and the conventional flash memory recording control method has a problem that the writing processing speed is slow.
[0033]
On the other hand, when the writing of the data of one page is completed, before the process of copying all the pages of the post-order address of the page, the next write page address is in the block being written. Then, it is determined whether or not the next write page address is a post-order address in the block being written and if the next write page address is in the post-order address of the page in which the write operation has been completed. After copying the data of the page up to the page address, the data of the next write page may be written.
[0034]
According to this write control method, it is possible to increase the speed of writing data to the flash memory.
[0035]
However, in a management area called a TOC area of the flash memory, data having a predetermined content is written in a predetermined address order. The rewriting of data in page units in the TOC area is not always performed in accordance with the address order, but is generally performed in a random address order, as described later.
[0036]
Therefore, even if the improved recording control method as described above is used, the effect of improving the writing speed of the TOC area is small.
[0037]
If the writing or rewriting processing time in the TOC area is long, for example, when a flash memory is used as a recording medium, the response to the operation becomes poor at the end of recording, at a stop operation, and the like. There has been a problem that the merchantability of the device is significantly impaired.
[0038]
In view of the above, the present invention provides a recording area in which data having a predetermined content is written in a predetermined address order, such as a TOC area, in a recording medium such as a flash memory. It is an object of the present invention to provide a recording control method capable of increasing the write processing speed as a recording control method.
[0039]
[Means for Solving the Problems]
In order to solve the above-described problems, a recording control method for a recording medium according to the present invention includes:
A predetermined memory in which data having a predetermined content is written in a predetermined address order on a recording medium that needs to be written in an address order for each data group having a predetermined number of data. A recording control method for an area,
In response to a write instruction for each of the data groups, each of the data groups is converted from an original address position to be originally written in the predetermined memory area to a conversion address position in the memory area in an address order, In the predetermined memory area, writing for each data group is performed sequentially,
Holds information indicating the correspondence between the original address position and the translated address position
It is characterized by the following.
[0040]
According to the present invention having the above-described configuration, data according to a write instruction for each data group with respect to a random address position is not written at an original address position as specified, but in a predetermined memory area in address order. The data is sequentially written in such a conversion address position. Therefore, writing for each data group is performed at a very high speed.
[0041]
Then, information indicating the correspondence between the original address position and the converted address position is held, for example, as table information. Therefore, even if written as described above, reading of data from a predetermined memory area can be performed based on the information indicating the held correspondence.
[0042]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of a recording control method and apparatus of a recording medium according to the present invention will be described with reference to the drawings, taking as an example a case where the method is applied to an IC (Integrated Circuit) recorder.
[0043]
FIG. 3 is a block diagram showing a configuration example of an IC recorder to which this embodiment is applied.
[0044]
In the IC recorder shown in FIG. 3, a control unit 1 constituted by a microcomputer controls a flash memory 2 as a recording medium and a display control on an LCD (Liquid Crystal Display) 3 as an example of a display element. , An operation input unit interface 6 for connecting the operation input unit 5 to the control unit 1, and a USB (Universal Serial Bus) interface 7.
[0045]
In this example, the microcomputer constituting the control unit 1 includes a CPU (Central Processing Unit) 11, a program ROM (Read Only Memory) 12, and a work area RAM (Random Access Memory) 13. Of course, a microcomputer in which the program ROM 12 and the work area RAM 13 are external to the CPU can be used.
[0046]
The components including the control unit 1 and the flash memory 2 constitute the embodiments of the recording medium recording control device according to the embodiment.
[0047]
In the IC recorder of this example, the audio signal from the microphone 21 is supplied to the recording processing unit 23 through the amplifier 22. The recording processing unit 23 converts the audio signal into a digital signal and performs data compression under the control of the control unit 1.
[0048]
When receiving the recording instruction from the operation input unit 5 through the operation input unit interface 6, the control unit 1 receives the audio data from the recording processing unit 23 and writes the audio data into the flash memory 2.
[0049]
Further, upon receiving a reproduction instruction from the operation input unit 5 through the operation input unit interface 6, the control unit 1 reads out audio data from the flash memory 2 and sends it to the reproduction processing unit 24. The reproduction processing unit 24 decompresses the received audio data under the control of the control unit 1 and returns the digital audio signal to an analog audio signal. Then, the reproduction processing unit 24 supplies the analog audio signal via the amplifier 25 to, for example, an audio signal output terminal to which an earphone is connected.
[0050]
The control unit 1 performs a predetermined display on the screen of the LCD 3 via the display control unit 4.
[0051]
Further, in the IC recorder of this example, for example, a personal computer can be connected to the USB connector 8 via a USB cable. Then, the control unit 1 reads out the audio data recorded in the flash memory 2 and transfers the data to the personal computer through the USB interface 7 or receives the data from the personal computer through the USB interface 7 and sends the data to the flash memory 2. Can be written.
[0052]
In this example, audio data written to the flash memory 2 can be managed for each message, and a text comment can be added to the audio data for each message. Has been. The character comment can be displayed on the screen of the LCD 3.
[0053]
The memory area management in the flash memory 2 in this case will be described. FIG. 4 is an explanatory diagram of a memory area of the flash memory 2 of this example. In FIG. 4, “BANK0” and “BANK1” and “EXTERNAL” are TOC areas. “PCM DATA” is an area in which audio data is written.
[0054]
“EXTERNAL” is an area where a text comment is written. In this example, the characters that can be input are 256 bytes and are assigned to one page for each message of the audio data. That is, a text comment for one business is assigned to one page.
[0055]
Each of “BANK0” and “BANK1” includes “FOLDER INDEX ADDRESS STAGE”, “EXTERNAL MAP”, “BLANK MAP”, and “REVISION”.
[0056]
“FOLDER INDEX ADDRESS STAGE” indicates where in the “PCM DATA” area the audio data for each message is located (in page units), and where in the “EXTERNAL” area is the text comment corresponding to the audio data. Stores information for managing (per page).
[0057]
The “EXTERNAL MAP” stores information for managing how a text comment is written in the “EXTERNAL” area and which page is a free area.
[0058]
“BLANK MAP” stores information on how audio data is written in “PCM DATA”. “REVISION” manages a number indicating the number of revisions of “BANK0” and “BANK1”.
[0059]
In the case of the IC recorder of this example, application software for writing a character comment is mounted on a personal computer connected through the USB interface 7. In the application, a text comment writing field is displayed on the screen of the personal computer for each of a large number of messages stored in the flash memory 2, and the text comment is input to the writing field.
[0060]
Then, the input character comment data is transferred from the personal computer to the IC recorder through the USB interface 7, and the control unit 1 writes the transferred character comment data in the “EXTERNAL” area of the flash memory 2. . In this case, the control unit 1 searches an empty area and writes a character comment in the “EXTERNAL” area with reference to “EXTERNAL MAP”. However, in this example, it is determined that writing is performed in the "EXTERNAL" area in the order of address number, starting from the empty page area having the first priority.
[0061]
It should be noted that there are two “BANK0” and “BANK1” in order to store the immediately preceding TOC information in one of them so that it can always return to the previous state. In other words, even if a sudden power-off occurs while the TOC is being rewritten, it is only one BANK that has been rewritten and always returns to the previous BANK information that has not been rewritten. be able to.
[0062]
Further, by referring to the number indicating the number of revisions stored in the area of “REVISION”, it is possible to know which of “BANK0” and “BANK1” is older and which is new TOC information. be able to.
[0063]
FIG. 5 shows an example of the detailed format of the TOC information written in one of the areas “BANK0” and “BANK1” (hereinafter referred to as a BANK area). This is for one block. As shown in FIG. 5, in the BANK area, data having a predetermined content is recorded at a predetermined physical address in page units.
[0064]
Actually, in consideration of the fact that the use of the flash memory 2 causes an area that cannot be used as a memory area, the BANK area is not fixed to a fixed physical address, but is a logical area defined as a BANK area. The above address is managed so that a physical address actually used as a BANK area is associated with the address. In this specification, for convenience of explanation, the BANK area includes a word “physical address”. It will be used as it is.
[0065]
Next, an example of how the BANK area is used and an example of data update will be described with reference to FIGS.
[0066]
FIG. 6 shows an example of how the BANK area is used, which is a case where an audio data file is managed. In FIG. 6, in the “EXTERNAL” area and the “PCM DATA” area, squares indicated by numbers “0”, “1”, “2”,. An example of a recorded page address position is shown. At each address position, character comment data is recorded in the “EXTERNAL” area, and audio data is recorded in the “PCM DATA” area.
[0067]
In the “FOLDER INDEX ADDRESS STAGE” area, the location page of the audio data in the “PCM DATA” area and the location page of the character comment data in the “EXTERNAL” area are listed for each message. The indicated information has been written.
[0068]
For example, the description “address0,3: Info4” of the first message indicates that the audio data of the message is recorded at the page address positions “0” and “3” in the “PCM DATA” area. Indicates that the character comment data is recorded at the page address position “4” in the “EXTERNAL” area.
[0069]
In the “EXTERNAL MAP” area, information indicating how to use the recording position in page units in the “EXTERNAL” area is recorded. In the area of “BLANK MAP”, information indicating how to use the recording position in page units in the area of “PCM DATA” is recorded.
[0070]
Next, some examples in the case where BANK data is updated will be described. In the example described below, when the data is recorded in the state as shown in FIG. 6, the updated result data created from the original data that was in “BANK0” is written in “BANK1,” and “BANK1.” Is updated to the new number.
[0071]
FIG. 7 shows a case where the order of the first message and the third message in the “FOLDER INDEX ADDRESS STAGE” area of FIG. It is. 7 to 11, the area of “FOLDER INDEX ADDRESS STAGE” is indicated as “INDEX & ADDRESS” due to the space of the drawing.
[0072]
When the order of the messages is changed, in the detailed format of FIG. 5, necessary page data of “FOLDER DATA” and “ADDRESS DATA” is rewritten, and write commands are generated in a random order.
[0073]
FIG. 8 shows a case where the fourth message in the area of “FOLDER INDEX ADDRESS STAGE” in FIG. 6 is divided into two in a case where the recording is performed in a state as shown in FIG.
[0074]
In this case, in the detailed format of FIG. 5, it is necessary to rewrite and add necessary page data out of “FOLDER DATA” and “ADDRESS DATA” and rewrite “EXTERNAL DATA”.
[0075]
FIG. 9 shows a case where the third message and the fourth message in the “FOLDER INDEX ADDRESS STAGE” area of FIG. 6 are combined in the case where the recording is performed in the state as shown in FIG. 6.
[0076]
Also in this case, in the detailed format of FIG. 5, it is necessary to rewrite and add necessary page data of “FOLDER DATA” and “ADDRESS DATA” and rewrite “EXTERNAL DATA”.
[0077]
FIG. 10 shows a case where a message is added in the case where the information is recorded in the state as shown in FIG.
[0078]
In this case, in the detailed format of FIG. 5, it is necessary to rewrite and add necessary page data of “FOLDER DATA” and “ADDRESS DATA”, and to rewrite “BLANK DATA” and “EXTERNAL DATA”. .
[0079]
FIG. 11 shows a case where a message is deleted in a case where the message is recorded as shown in FIG.
[0080]
In this case, in the detailed format of FIG. 5, it is necessary to rewrite necessary page data of “FOLDER DATA” and “ADDRESS DATA” and rewrite “BLANK DATA” and “EXTERNAL DATA”.
[0081]
Updating of the BANK area as described above is performed by updating, adding, and deleting only necessary page data. A page write command is not generated in the order of addresses. Will be started.
[0082]
Therefore, in the conventional write control method, it is necessary to perform rewriting in units of blocks each time data of one page is rewritten, and to perform a process of repeating page copy in one block. This takes a very long time and causes a problem that the response to the user operation is poor.
[0083]
[Write Control in TOC Area in Embodiment]
Next, write control of data in the TOC area of the flash memory 2 in this embodiment will be described.
[0084]
FIG. 12 is a diagram for explaining a write control method in the TOC area in this embodiment. The left side of FIG. 12 shows a BANK area on the flash memory 2, and BPA [0], BPA [1], BPA [2], BPA [3], BPA [4]... BPA [i] ( i is a numerical value indicating the page number from the beginning of the BANK area, and i = 0, 1, 2,...) is the physical page address of the BANK area.
[0085]
This physical page address BPA [i] corresponds to “address” in FIG. 4, and each data shown in the “entry” column shown in FIG. 5 is originally written at each address position. Should be.
[0086]
However, in this embodiment, control is not performed such that the data shown in the “entry” column shown in FIG. 5 is written to each of the physical page addresses BPA [i] of the BANK area. The data to be written to the write page address is written in order from the first page address (physical page address) of the BANK area in the order in which the write page address command is generated.
[0087]
That is, when the microcomputer 1 generates a write page address for the BANK area of the flash memory 2, the data to be written to the write page address is changed from the physical page address (original address position) to which the BANK area should originally be written. Is converted into a physical page address (conversion address position) in the address order, and the converted physical page address is sequentially written.
[0088]
However, in this embodiment, in FIG. 5, the "INDEX HEADER" of the first page in which the "REVISION" number is written is fixedly written to the first physical page address of the BANK area. The “LAST V Page” of the last page is also fixedly written to the last physical page address of the BANK area.
[0089]
By doing so, the page data is written in order from the top of the physical page address in the BANK area. After the writing of one page is completed, the page data of the lower-order page address in one block is copied. Instead, the writing of the next page can be continued. Therefore, data can be written to the TOC area at high speed.
[0090]
However, as it is, the contents of the entry in the BANK area in FIG. 5 cannot be read. Therefore, in this embodiment, the data of the write page address for the BANK area given from the microcomputer 1 forms and retains information indicating the correspondence in the physical page address BPA [i]. I do.
[0091]
In this embodiment, the following page address conversion table is used as the information indicating the correspondence.
[0092]
In this embodiment, the write page address for the BANK area provided from the microcomputer 1 will be referred to as a “logical page address”. In FIG. 12, LPA [0], LPA [1], LPA [2], LPA [3], LPA [4]... LPA [j] (j is the number of the page from the top of the BANK area. .. Are j = 0, 1, 2,...) Are the ethical page addresses.
[0093]
The logical page address is a virtual page address recognized by the upper layer as “the data shown in the“ entry ”column of FIG. 4 has been written there in the BANK area”. If each data of the entry in FIG. 5 is written to the physical page address of the BANK area as in the conventional case, BPA [i] = LPA [j] (i = j). However, as described above, in this embodiment, such writing is not performed in the BANK area.
[0094]
In this embodiment, as shown on the right side of FIG. 12, when writing to the BANK area, the data of this logical page address LPA [j] is stored in the RAM 13 of the microcomputer 1 in any physical page address BPA [ The page data is written into the BANK area while forming a correspondence table (hereinafter referred to as a page address conversion table) written in [i].
[0095]
In this case, since the physical page address BPA [i] and the logical page address LPA [j] need only be managed in page units, in this example, offset numbers in page units from the beginning of the BANK area are used. . Therefore, since BANK0 and BANK1 are 32K bytes as shown in FIG. 5, the physical page addresses BPA [i] to be written in the page address conversion table for each of BANK0 and BANK1 are "0" to "63". One of these values is stored. When the value stored in the page address conversion table is “0xff”, it means that the page has not been written yet.
[0096]
As described later, in this embodiment, the page address conversion table formed in the RAM 13 is written in “LAST V Page” of the BANK area. In this example, the “LAST V Page” of the BANK area is fixedly written to the last physical page address of the BANK area as described above, so that the page address conversion table can be referred to quickly. .
[0097]
The page address conversion table may be written in the page area converted using the page address conversion table of the BANK area, or may be written in another memory area in the flash memory 2 or in the outside of the flash memory 2. It is needless to say that the data may be written and stored in the non-volatile storage means.
[0098]
Next, a write (rewrite) processing procedure in the BANK area when rewriting the TOC area of the flash memory 2 will be further described.
[0099]
FIGS. 1 and 2 are flowcharts of a processing operation when data is written to the TOC area of the flash memory 2 according to the present embodiment. This processing is mainly performed by the CPU 11 of the control unit 1 in accordance with the program of the ROM 12. It is described.
[0100]
That is, the control unit 1 determines whether or not a write instruction to the TOC area has been issued (step S101), and when it is determined that the write instruction has not been issued, executes other processing (step S102).
[0101]
When it is determined in step S101 that a write instruction has been issued, the CPU 11 erases the data in the older BANK area of BANK0 and BANK1 to make it an empty area, and also stores the above-described logical page address LPA [ j]], an area of the page address conversion table indicating the correspondence of the physical page address BPA [i] to the corresponding page address is prepared. It is initialized to “0xff” (step S103).
[0102]
Next, the CPU 11 writes “INDEX HEADER” including the “REVISION” number into the first physical address BPA “0” of the vacant BANK area (step S104).
[0103]
Next, the CPU 11 recognizes the logical page address LPA [j] as a write page address (step S105), and writes an empty BANK area in which the data PD (LPA [j]) of the logical page address LPA [j] is to be written. Of the physical page address BPA [i] is determined. As the physical page address BPA [i] corresponding to the logical page address LPA [j], a physical page address next to the previously written physical page address in the empty BANK area (a physical page address in the next lower order of the page address order) is assigned. (Step S106).
[0104]
Next, in the page address conversion table prepared in the RAM 13, the CPU 11 writes the obtained physical page address of the empty BANK area to the address of the RAM 13 corresponding to the logical page address specified in step S105 (step S107). ).
[0105]
Then, the data PD (LPA [j]) of the logical page address LPA [j] designated to be written is written to the physical page address of the free BANK area obtained in step S106 (step S108).
[0106]
Next, the CPU 11 determines whether or not the write page address instruction for the BANK area has been completed (step S109). If it is determined that the write page address instruction has not been completed, the process returns to step S105, and repeats the processing from step S105.
[0107]
If it is determined in step S109 that the write page address instruction for the BANK area has been completed, an unwritten logical page address of “0xff” is searched in the page address order on the page address conversion table of the RAM 13. (Step S111 in FIG. 2).
[0108]
Next, the CPU 11 sets the next physical page address in the free BANK area as the physical page address of the free BANK area to which the data of the detected unwritten logical page address is to be written (the page address order is It is determined by allocating the next lower physical page address (step S112).
[0109]
Then, in the page address conversion table of the RAM 13, the CPU 11 writes the physical page address obtained in Step S112 to the detected unwritten logical page address (Step S113).
[0110]
Next, the CPU 11 writes the data at the page address corresponding to the logical page address in the BANK area of the rewriting source to the physical page address of the empty BANK area obtained in step S112 (step S114). That is, the page data is copied.
[0111]
Next, the CPU 11 determines whether or not the writing up to the last page of the BANK area has been completed on the page address conversion table of the RAM 13 (step S115). The process returns to step S111 and the subsequent steps are repeated.
[0112]
If it is determined in step S115 that the writing up to the last page of the BANK area has been completed, the page address conversion table formed on the RAM 13 is written in the last page of the empty BANK area (step S116). Thus, the writing to the BANK area of the TOC area is completed.
[0113]
Next, the above processing procedure will be described more specifically with reference to FIG. For example, as shown in FIG. 11, the microcomputer 1 generates a write page address (logical page address) for the BANK area in the order of (1), (2), (3), (4). In this case, a procedure for writing to the BANK area will be described.
[0114]
When the write page of the BANK area is determined as the (1) -th logical page address LPA [30], the control unit 1 should write the data PD (LPA [30]) of the logical page address LPA [30]. The second physical page address BPA [1] of the BANK area is detected as the physical page address of the BANK area.
[0115]
Therefore, the control unit 1 writes the physical page address BPA [1] to the logical page address LPA [30] in the page address conversion table of the RAM 13. Prior to this, the data PD (LPA [0]) of “INDEX HEADER” has been written to the physical page address BPA [0] of the BANK area, and the logical page address LPA [0] of the page address conversion table has been written. , Physical page address BPA [0] is written.
[0116]
Next, the control unit 1 writes the data PD (LPA [30]) to be written to the logical page address LPA [30] at the physical page address BPA [1] in the free BANK area of the flash memory 2. Control.
[0117]
Next, when the (2) -th logical page address to be written to the BANK area is determined as the logical page address LPA [8], the control unit 1 sets the data PD (LPA [8]) of the logical page address LPA [8]. ]) Is to be written, the second physical page address BPA [2] of the BANK area is detected as the physical page address of the BANK area.
[0118]
Then, the control unit 1 writes the physical page address BPA [2] to the logical page address LPA [8] in the page address conversion table of the RAM 13.
[0119]
Next, the control unit 1 writes the data PD (LPA [8]) to be written to the logical page address LPA [8] to the physical page address BPA [2] in the free BANK area of the flash memory 2. Control.
[0120]
Also, the physical page address BPA [3] of the free BANK area is assigned to the (3) th write page address (logical page address) LPA [20], and the logical page address LPA [8] in the page address conversion table. ], The physical page address BPA [3] is written, and the data PD (LPA [8]) to be written to the logical page address LPA [8] is written to the physical page address BPA [2] in the empty BANK area. It is.
[0121]
Hereinafter, in the same manner, the physical page address of the empty BANK area is allocated in the order of the generation of the write page address, and the physical page address allocated to the logical page address of the page address conversion table is written. , The page data to be written to the logical page address is written to the assigned physical page address of the free BANK area.
[0122]
In this embodiment, a page address conversion table formed in the RAM 13 is written in the last page.
[0123]
Next, reading of TOC information from the BANK area will be described.
[0124]
At the time of reading, the control unit 1 first reads the page address conversion table of the last page of the BANK area of the flash memory 2 and writes it in the RAM 13.
[0125]
Next, every time a read logical page address is generated, the control unit 1 refers to the page address conversion table on the RAM 13 to check the physical address of the BANK area where the data of the specified read logical page address is recorded. The page address is obtained, and the flash memory 2 is controlled so as to read the data of the specified read logical page address from the obtained physical page address.
[0126]
As described above, the TOC information written in the BANK area is read without any trouble.
[0127]
In this embodiment, only the BANK area in which “LAST V Page” exists is valid at the time of a reset start when the power is cut off during writing in the TOC area. In the normal use state, the BANK area with the larger “REVISION” number is used as valid.
[0128]
[Other embodiments]
In the above embodiment, the information indicating the correspondence between the logical page address and the physical page address is recorded in the page address conversion table in the BANK area. However, the page address conversion table is written in the BANK area. Instead, you can do the following:
[0129]
Also in this example, while forming a page address conversion table on the RAM 13 at the time of writing, page data is sequentially written in the physical page address of the BANK area in the order of the address, as in the above-described embodiment. .
[0130]
However, in this embodiment, the page address conversion table is not written in the last page of the BANK area. Instead, as shown in FIG. 13, a corresponding logical page address is written to a spare area of page data to be written to each physical page address of the BANK area. As described above, the logical page address is an offset number from the head of the BANK area, and can be represented by one byte since a value of “0” to “63” is used.
[0131]
In the case of this example, at the time of reading, all pages of the BANK area are once read, the logical page addresses included in the respective page data are read, and the page address conversion table is reconfigured on the RAM 13. . Then, using the reconfigured page address conversion table on the RAM 13, data in the BANK area is read in the same manner as in the above-described embodiment.
[0132]
[Modification]
Although the above embodiment has been described in connection with the case where the recording medium is a NAND flash memory, the present invention is directed to all the recording media in which the same address control as that of the NAND flash memory must be performed at the time of writing in the TOC area. Applicable to
[0133]
Further, it goes without saying that the electronic apparatus to which the present invention is applied is not limited to an IC recorder. A recording medium such as a flash memory is not limited to a case where the recording medium is built in an electronic device. For example, the flash memory may be a card-type memory and may be insertable and removable.
[0134]
Further, in the description of the above-described embodiment, the management of the write control is performed using the logical-physical address conversion table.
[0135]
Also, in the above description, a case was described in which, in a block, writing was performed in ascending order from the page with the smallest address. However, the present invention is applicable to a case where writing is performed in descending order from the page with the largest address. Can be similarly applied.
[0136]
【The invention's effect】
As described above, according to the present invention, a high-speed recording area in which data having predetermined contents is written in a predetermined address order, such as a TOC area of a flash memory, is used. Can be written.
[Brief description of the drawings]
FIG. 1 is a part of a flowchart for describing an embodiment of a recording control method for a recording medium according to the present invention.
FIG. 2 is a part of a flowchart for describing an embodiment of a recording medium recording control method according to the present invention.
FIG. 3 is a diagram illustrating a configuration example of an IC recorder to which an embodiment of a recording control method for a recording medium according to the present invention is applied;
FIG. 4 is a diagram for explaining a memory area structure of a flash memory.
FIG. 5 is a diagram showing a detailed example of data recorded in a TOC area of a flash memory.
FIG. 6 is a diagram for explaining the contents of TOC data recorded in a flash memory.
FIG. 7 is a diagram for explaining an example of rewriting TOC data recorded in a flash memory.
FIG. 8 is a diagram for explaining an example of rewriting TOC data recorded in a flash memory.
FIG. 9 is a diagram for explaining an example of rewriting TOC data recorded in a flash memory.
FIG. 10 is a diagram for describing an example of rewriting TOC data recorded in a flash memory.
FIG. 11 is a diagram for explaining an example of rewriting TOC data recorded in a flash memory.
FIG. 12 is a diagram illustrating a processing procedure of an embodiment of a recording medium recording control method according to the present invention.
FIG. 13 is a diagram for explaining another embodiment of a recording control method for a recording medium according to the present invention.
FIG. 14 is a diagram illustrating a data configuration of a NAND flash memory.
FIG. 15 is a diagram for explaining a conventional recording control method for a NAND flash memory.
FIG. 16 is a flowchart for explaining a conventional recording control method for a NAND flash memory.
FIG. 17 is a diagram for explaining a conventional recording control method for a NAND flash memory.
And FIG. 18 is a flowchart illustrating an example of a reset process in a conventional recording control method for a recording medium.
[Explanation of symbols]
1. Control unit 2. Flash memory

Claims (11)

A predetermined memory in which data having a predetermined content is written in a predetermined address order on a recording medium that needs to be written in an address order for each data group having a predetermined number of data. A recording control method for an area,
In response to a write instruction for each data group, each data group converts an original address position to be originally written in the predetermined memory area into a conversion address position in the predetermined memory area in an address order. Thereby, in the predetermined memory area, the writing for each data group is performed sequentially,
A recording control method for a recording medium, wherein information indicating a correspondence relationship between the original address position and the converted address position is held. The recording control method for a recording medium according to claim 1,
A recording control method for a recording medium, wherein the information indicating the correspondence between the original address position and the converted address position is written in the predetermined memory area. The recording control method for a recording medium according to claim 1,
A recording control method for a recording medium, wherein information indicating the correspondence between the original address position and the converted address position is written to a fixed address position in the predetermined memory area. The recording control method for a recording medium according to claim 1, 2 or 3,
The recording control method for a recording medium, wherein the information indicating the correspondence between the original address position and the converted address position is table information. The recording control method for a recording medium according to claim 1,
The information indicating the correspondence between the original address position and the translated address position is information for specifying the original address position in the predetermined memory area, which is included in the data for each data group. A recording control method for a recording medium. A predetermined memory in which data having a predetermined content is written in a predetermined address order on a recording medium that needs to be written in an address order for each data group having a predetermined data number. A recording control device for the area,
A conversion address position detecting unit that obtains a conversion address position in an address order with respect to a previous write address position in the memory area when receiving a write instruction for each data group;
Correspondence information forming means for forming information indicating the relationship between the translated address position obtained by the translated address position detecting means and the original address position where each data group is to be written in the predetermined memory area. ,
A data writing unit that writes data in the predetermined memory area at the conversion address position obtained by the conversion address position detection unit;
After the data is written by the data writing unit, the conversion address position detecting unit, the correspondence information forming unit, and the data writing unit are repeated until writing to the predetermined memory area is completed. Control means for controlling;
A recording control apparatus for a recording medium, comprising: The recording control device for a recording medium according to claim 6,
A recording control device for a recording medium, further comprising: a unit for writing information formed by the correspondence information forming unit into the predetermined memory area. The recording control device for a recording medium according to claim 6,
A recording control apparatus for a recording medium, comprising: means for writing the information formed by the correspondence information forming means at a fixed address position in the predetermined memory area. The recording control apparatus for a recording medium according to claim 6, 7, or 8,
The recording control device for a recording medium, wherein the information formed by the correspondence information forming means is table information. The recording control device for a recording medium according to claim 6,
The recording control apparatus for a recording medium, wherein the correspondence information forming means includes information for specifying the original address position in the predetermined memory area in the data for each data group. . An electronic apparatus comprising the recording control device for a recording medium according to claim 6.

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