JPS62197874A - Image processor - Google Patents

Abstract

PURPOSE:In superposing of a plural number of image data, to obviate such defects as the image below being seen at the highlight part of the topmost superposed image, by providing an image processes enabling selective output of picture element of the topmost image. CONSTITUTION:In case the picture elements of a highlight part are superposed at the topmost layer, (n) bit data on highlight part are all zero for those picture elements. However the picture element data S3' is equal to '1' with respect to the internal picture elements of an image area extracted by an area extracting part 4-3. Therefore, picture element data S3 containing (n) bits all set at '0' is outputted selectively via an AND gate G5 and an OR gate G6 via a logic circuit of a picture processing part 6 regardless of the state of picture element data S2'. This can avoid such a defective fact that the images set at a lower position are seen through.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus that can superimpose a plurality of grayscale images without any inconvenience.

[Problems with the prior art] Conventionally, when superimposing two S light images, for example, in 4i5 minutes where the images overlap, pixel data of only one is used,
If the superimposition process is performed so that one of the images is on top, the following problems occur.

First, a case will be described in which a grayscale image as shown in FIG. 2(1) and a grayscale image shown in FIG. 2(2) are superimposed. Both images are data consisting of 1 pixel and n bits. Figure 2 Q)
The area designated as P indicates a highlighted portion caused by reflection of a light ray, etc., and it is assumed that all n bits of the pixel data of that area P are "0".

For such images in Figure 2 (1) and (2), if only one pixel data has a "1" bit, that pixel data is left, and both pixel data have a "1" bit. If the data of the superimposed image is created using the method of leaving the pixel data of one of the images to clarify the vertical relationship between the two images and displaying it on the display, an image like the one shown in Figure 2 (3) will be created. become. That is, the image shown in FIG. 2 (1), which should not originally be displayed, is displayed in the area P, and the image underneath becomes transparent.

[Object of the Invention] The present invention has been made based on the above-mentioned points, and aims to provide an image processing device that does not have the above-mentioned drawbacks. a stored image memory; and an area memory that stores binary data created by extracting an outline of an area where an image exists from the image data stored in the image memory and filling in the inside of the outline. , when multiple image data are superimposed, even if all n bits of pixel data of the image to be superimposed on top are "0", if the bit of the pixel in the area memory is "1", and an image processing unit that selectively outputs the pixel data of the image to be superimposed on the top.

[Configuration of the Invention] FIG. 1 is a block diagram showing an embodiment of an image processing apparatus of the present invention. 1 is the keyboard, 2 is the IIJI W section, 3
-1.3-2.3-3 is an image memory that stores n-bit image data per pixel, and 4-2.4-3 extracts the image area of the image memory 3-2.3-3. and an area extraction unit that creates data that fills out the area, 5-2
．． 5-3 is an area memory for storing the data extracted by the area extraction unit 4-2.4-3, 6 is an image processing unit that performs processing such as image synthesis, 7 is a CRT controller, and 8 is a display unit. .

FIG. 3 is a circuit diagram for performing processing in the image processing section 6. As shown in FIG. G+-Gs is an AND gate, G6 is an OR gate,
07 to G9 are NOT gates.

[Operation of the invention] Next, the operation of the invention will be described. In the following description, an example will be described in which three images are superimposed, but the principles of the present invention can be easily applied to cases in which four or more images are superimposed.

FIG. 4(1) is a diagram showing both image data stored in the image memory 3-1. Further, FIG. 4(3)-A is a diagram showing image data stored in the image memory 3-2, and FIG. 4(3)-A is a diagram showing image data stored in the image memory 3-3.

First, from the keyboard 1, select the image memory 3-1゜3-2.
3-3 is instructed to superimpose the image data stored in advance. Based on the instruction, the following processing is performed under the control of the control unit 2.

In addition, in the superimposition process, the topmost image data is the image data stored in the image memory 3-3, and the image data stored in the image memory 3-2.3 is
-'l are superimposed in the order of the image data stored.

First, the image data in the image memory 3-2.3-3 is sent to the area extraction section 4-2.4-3.

The area extraction unit 4-2.4-3 extracts the outline of the area where the image exists from the sent image data, and then creates 2[ data by filling in the inside of the outline and stores it in the area memory. 5-2. Send to 5-3 and store. Also, the area extraction unit 4
-2.4-3, or when you want to find the area of one image from multiple images in image memory 3-2.3-3, use a pointing device such as a mouse (not shown). , image memory 3-2゜3
-3 W4 area is designated and the filled data is stored in the area memory 5-2.5-3.

Figure 4 ■-B and (3)-B perform such processing,
FIG. 4 is a diagram illustrating the binary data extracted from the regions in which the image data of FIGS. Figure 4 (2)-8,
(3) The area filled in black with -8 is bit “1”
This is the part.

After that, from the image memory 3-1.3-2.3-3 and the area memory 5-2.5-3, one pixel worth of data stored in each memory is transferred to 8+ + in FIG.
82 + 83 + 82 ' + S:l ' The image [11 is sent to the science department 6.

The data input to the image processing unit 6 is superimposed pixel by pixel according to the logic circuit shown in FIG.
The processing in the image processing unit 6 when three images in FIGS. (1), (2)-8, and (3)- are folded will be specifically described.

First, a case where "1" bits exist in all n-bit pixels supplied as S+, 82.83 will be explained. In this case, the data S2'S3' of the pixel from the area memory 5-2.5-3 is S2'=1 S co' -1. Therefore, the logic circuit shown in FIG. 3 selectively outputs 83 pixel data via the AND gate Gs and the OR gate G6.

Next, a case will be described in which the pixels of the highlighted portion are superimposed on the top, as in the P section of FIG. 4(3)-A. All n bits of pixels in this part are rOJ data. However, since it is a pixel inside the image area extracted by the area extraction unit 4-3, it is S3'-1.

Therefore, regardless of 32', this data is processed by the logic circuit shown in FIG.
It is selectively outputted via OR gate G6. Therefore, processing such as the part P in FIG. 2 (3) in which the underlying image is seen through is not performed.

In this way, when 83'=1, this signal acts as an inhibiting signal for S+ and Sl, so it is visually It is displayed as if it were the frontmost image. at the same time,
If Sz'=1, this signal acts as an inhibiting signal. Therefore, the image sent at 82 is displayed with priority over the image from Sl. Visually S! Displayed as a full-scale image.

The data processed pixel by pixel as described above is
Under the control of the CRT controller 7, the image is displayed on the display unit 8 as shown in FIG.

The embodiments of the present invention have been described in detail above. In the above description, by appropriately changing the storage contents of the image memories 3-1 to 3-3, it is possible to freely change the visual context of each image on the display section 8.

Further, in the above embodiment, the case where the processing results are displayed on a CRT has been described, but the present invention can also be applied to cases where the processing results are outputted from a printer or stored in a storage means.

[Effects of the Invention] As explained in detail above, the present invention can solve the conventional drawback that when performing superimposition processing on gray scale images, the underlying image is visible in the highlighted part as described above. The effect is great because it can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the image processing device of the present invention, FIG. 2 is a diagram showing an example of image superimposition processing in a conventional image processing device, and FIG. 3 is a block diagram showing an example of image superimposition processing in a conventional image processing device. As an example of a circuit diagram, FIG. 4 is a diagram showing an example of an image subjected to superimposition processing according to the present invention, and FIG. 5 is a diagram showing an example of the result of superimposition processing according to the present invention. 1...Keyboard 2...Control unit 3-1.2.3...Image memory 4-2.3...Area extraction unit 5-2.3...Area memory 6...Image Processing section 7...CRT controller 8...Display section

Claims (1)

[Claims] An image memory that stores image data of 1 pixel and n bits, and an outline of an area where the image exists is extracted from the image data stored in the image memory, and the inside of the outline is extracted. When superimposing multiple image data with area memory that stores binary data created by filling, even if all n bits of pixel data of the image to be superimposed on top are "0",
an image processing unit that selectively outputs the pixel data of the image to be superimposed on the top when the bit of the pixel in the area memory is "1".