JPS62196760A - Data transfer system for parallel computer - Google Patents

Abstract

PURPOSE:To make switching of a processor of destination of transfer by making a host computer transfer the number of processor of destination of transfer and data to be transferred in a set to all processors and deciding whether each processor takes in data or not. CONSTITUTION:When transferring data, a host computer 1 makes the number of processor of destination of transfer and data to be transferred a set and outputs to all processors 2, 3,...n by the same data transfer line. On the other hand, processors 2, 3,...n compare received number of processor and the content of its own processor number register by a coincidence deciding circuit 24, and store received data in a place of reception indicated by an address register in its own memory only for a conformable processor. The value of an address register 25 is updated to receive next data.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is a parallel computer consisting of a host computer and a plurality of processors connected to the host computer, in which individual data is transferred from the host computer to any processor. Regarding the method.

[Conventional technology]

FIG. 2 is a block diagram of a parallel computer, including a host computer 1 and a plurality of processors 2, 3, 4, . ... n are all connected by the same data transfer line.

Conventionally, in such a configuration, the host computer 1
The data transfer setting method and the shared memory method are known as methods for transferring individual data from the processor 2 to each of the processors 2 to n.

In the data transfer path setting method, first, before data transfer,
The host computer 1 instructs all processors other than the transfer destination processor (referred to as processor 2) to prohibit data input from the host computer (data transfer path setting). Thereafter, the host computer 1 transfers data to all processors 2, 3 . ...Output to n. At this time, data input is prohibited except for the transfer destination processor 2, and only the processor 2 can obtain data from the host computer 1.

Next, in the shared memory method, as shown in FIG. 3, memories 21, 31 . . . . logical address spaces 12, 13 . . . corresponding to nl, respectively. ..., 1n are provided. When the host computer 1 transfers data to the processor 2, the host computer 1 specifies an address in the logical address space and executes an operation of writing data into the address space 12.

The addresses and data of this logical address space 12 are transferred to all processors 2゜3, . . . by the same data transfer line.
Output to n. In this case, processor 3゜4,...
n, the received addresses are respectively stored in memories 31, 41 .・
...Because it is outside the nl address space.

No data is written, and only the processor 2 can write data from the host computer 1 to the corresponding address in the memory 21.

[Problem that the invention seeks to solve]

In the above conventional technology, in the data transfer path setting method, it is necessary to set the data transfer path prior to data transfer.
Moreover, the setting time increases in proportion to the number of processors that require data transfer, which has the disadvantage of resulting in a large amount of wasted time. On the other hand, in the shared memory method, when the host computer writes data to the logical address space, the same data is simultaneously written to the memory of the transfer destination processor, which solves the problem of wasted time. As the memory capacity of the host computer increases or the number of processors increases, the logical address space within the host computer also increases.

The present invention has been made to solve the problems of the shared memory method described above, and even if the number of processors connected to the host computer and the memory capacity of each processor increase, the logic of the host computer remains unchanged. The object of the present invention is to provide a data transfer method that does not increase address space.

[Means for solving problems]

The present invention provides a parallel computer consisting of a host computer and a plurality of processors connected to the host computer, in which each processor has a memory attached to each processor, in addition to a memory for storing data transferred from the host computer. A self-processor number register for storing the number of the host processor and an address register for indicating the storage location of data transferred from the host processor are provided.

[For production]

When transferring data, the host computer outputs the transfer destination processor number and transfer data as a set to all processors via the same data transfer line. On the other hand, each processor compares the received processor number with the contents of its own processor number register, and only the processor with a match stores the received data in the storage location indicated by the address register in its own memory. Update the value of the address register to accommodate the data.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration diagram of an embodiment of the present invention. In FIG. 1, a host computer 1 and a plurality of processors 2, 3
．． . . . n are connected in parallel through the same connection wires 131 and 132. The host computer 1 includes a CPU 11 for data processing, and logical address spaces 12, 13, . . .
address register 121 and data register 122 that store addresses and data output from the CPU, respectively.
It consists of For example, the processor 2 also includes a own processor number register 22 that stores a number unique to the own processor, a transfer destination processor number register 23 that stores a transfer destination processor number output from the host computer 1, and an own processor number register 22 that stores a number unique to the own processor. A matching circuit 24 determines whether the contents of the transfer destination processor number and the contents of the register 23 match or do not match, and the host computer 1
It is composed of a memory 21 that stores data output from the memory 21 and an address register 25 that indicates the storage location. Other processors 2, 3 . . . . The configuration of n is also similar to that of processor 2.

Logical address space in host computer 1 12.13
．． in is processor 2, 3 . . . . There is a one-to-one correspondence with each of n. However, this logical address space 12,1
3. ...1n is the size of each processor 2, 3
．． . . . Corresponds to the memory capacity of one address of the memories 21, 31, . . . nl provided in n. For example, the size of the address space 12 is equivalent to the storage capacity of one address of the memory 21.

Therefore, data will be overwritten one after another in the same logical address space. This does not cause any problem because the logical address space is a virtual space.

The operation when the host computer 1 transfers data to the processor 2 will be described below.

In this case, the C:PUl 11 of the host computer 1 outputs processor number 2 to the address output line 112 and data to the data output line 113, and executes a data write operation to the logical address space 12. At the same time, the processor number 2 on the address output line 112 is stored in the address register 121, and the data on the data output line 113 is stored in the data register 122. Processor number 2 and data in this register 121, 122 are sent to all processors 2.3, . . . n through connection lines 131, 132. Of these, processor number 2 is stored in the transfer destination processor number register i2 (i=2.3...n) of each processor 2, 3...n.

On the other hand, the processor 2 uses the contents stored in the transfer destination processor number register 23 and the own processor number register 2.
In this example, the contents of 2 are sent to the match determination circuit 24 via signal lines 231 and 221 for comparison. Since the transfer destination processor number register 23 stores the own processor number 2, the match determination circuit 24 determines that there is a match. It will be judged. Therefore, the output line 241 of the match determination circuit 24 becomes ``1''.

The address register 25 operates, and the data on the connection line 132 is stored in the address (accommodation location) indicated by the address register 25 in the memory 21. Thereafter, the value of the address register 25 is increased by one. By incrementing this address register 25 by 1, when the host computer 1 transfers data to the processor 2 again, the next data will be stored in the next address of the memory 21.

Processors 3, 4. ... n also operates in the same way as above, but transfer destination processor number register 13 (i = 3.4
．． ...n) and the contents of the own processor number register 12 do not match, the data on the connection line 132 is not stored in each memory.

Note that the host computer 1 has a processor 3゜4,...
- When transferring data to n, the CPU 11 transfers data to the logical address spaces 13, 14 . . . . This is realized by performing an operation of writing data to 1n.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, when data is transferred from the host computer to each processor individually, the host computer transfers the transfer destination processor number and the data to be transferred as a set to all the processors. , the transfer destination processor is switched by determining whether each processor accommodates the above data (
This eliminates the need for transfer path setting), and prevents an increase in the time required for the switching due to an increase in the number of processors connected to the host computer. In addition, the logical address space required by the host computer can be significantly reduced to the number of processors x 1 address, and there is also the advantage of eliminating the need for memory address lines in the connection lines between the host computer and processors. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a schematic block diagram of a parallel computer, and FIG. 3 is a diagram illustrating a data transfer method of a conventional parallel computer. 1...Host computer. 2.3,4. ~n...processor, 12.13. ~n...Logical address space, 111...
・CPU, 121...Address register, 122
. . . Data register, 131, 132 . . . Connection line, 21, 31, 41. ~n1...Memory, 22
... Own processor number register, 23... Transfer destination processor number register, 24... Match determination circuit,
25...Address register. Figure 2 Figure 3

Claims (1)

[Claims] (1) In a parallel computer consisting of a host computer and multiple processors connected to the host computer, each processor is given a unique number, and the memory that stores data transferred from the host computer and its storage location are indicated. A register is provided in each processor,
When transferring data from a host computer to a certain processor, the host computer sends the data transfer destination processor number and the data to be transferred as a pair to all processors, and the processor side assigns the received processor number and its own processor. Only the processor whose unique number matches the one stores the data transferred from the host computer in the corresponding storage location indicated by the register in the memory, updates the value of the register, and transfers the data next time. A data transfer method for a parallel computer characterized by indicating a data storage location.