JPS62195158A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62195158A JPS62195158A JP61035158A JP3515886A JPS62195158A JP S62195158 A JPS62195158 A JP S62195158A JP 61035158 A JP61035158 A JP 61035158A JP 3515886 A JP3515886 A JP 3515886A JP S62195158 A JPS62195158 A JP S62195158A
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- bonding
- thickness
- conductive layers
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000008188 pellet Substances 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 abstract description 15
- 238000000034 method Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000002788 crimping Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体製造技術さらにはセラミンク封止の半
導体装置の製造技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor manufacturing technology, and more particularly to a manufacturing technology of a semiconductor device sealed with ceramic.
セラミック封止半導体装置については、特開昭５９−１
５０４５（ｌ公報に開示されており、その！
概要を第１図に示す。１はセラミック基板で、その中央
部にはキャビティ２が岑成され、半導体ペレット３が装
着されている。セラミック基板１上には、その側部に設
けられたり一ド４と接続する導電層５が形成されている
。６はペレット３の電。For ceramic sealed semiconductor devices, see Japanese Patent Application Laid-Open No. 59-1
5045 (disclosed in Publication No. 1, and the outline thereof is shown in FIG. 1. 1 is a ceramic substrate, a cavity 2 is formed in the center thereof, and a semiconductor pellet 3 is mounted. Ceramic substrate 1 A conductive layer 5 is formed on the side of the conductive layer 5 and connected to the conductive layer 4. Reference numeral 6 indicates the conductive layer 5 of the pellet 3.
袷と導電層５とを電気的に接続するボンディングワイヤ
である。７はパッケージ上部で、例えば低融点ガラス層
８を介して蓋体９が装着されている。This is a bonding wire that electrically connects the sleeve and the conductive layer 5. 7 is the upper part of the package, and a lid 9 is attached thereto, for example, with a low melting point glass layer 8 interposed therebetween.
〔発明が解決しようとする問題点］
ところが、上記技術を用いてリード数が非常に多い半導
体装置を製造すると、−ト記問題点が発生することが考
えられる。すなわち、電気メッキのさい導電層の表面の
縁部が円状に形成されるので導電層表面は底面に比べ゛
（その幅が狭く、リード数が多くなればなるほど導電層
の平坦部分の幅１１がより狭（なるため、ボンディング
ワイヤ６の圧着面積が十分確保できず、ボンディングワ
イヤの接合強度が弱くなる。従って、ボンディングワイ
ヤ５の断線不良が発生−する危険性が極めて高いことが
分かった。[Problems to be Solved by the Invention] However, if a semiconductor device having a large number of leads is manufactured using the above-mentioned technology, the problems described in (g) may occur. In other words, since the edge of the surface of the conductive layer is formed in a circular shape during electroplating, the surface of the conductive layer is narrower than the bottom surface (the width of the flat part of the conductive layer is narrower as the number of leads increases). As the bonding wire 6 becomes narrower, a sufficient crimping area for the bonding wire 6 cannot be ensured, and the bonding strength of the bonding wire becomes weaker. Therefore, it was found that there is an extremely high risk that the bonding wire 5 will break.
本発明の目的は、絶縁基板上に形成した導電層を介して
ボンディングワイヤと外部端子とを接続している半導体
装置のボンダビリティを向上できりる技術を提供するこ
とである。An object of the present invention is to provide a technique that can improve the bondability of a semiconductor device in which a bonding wire and an external terminal are connected through a conductive layer formed on an insulating substrate.
〔問題点を解決するための手段である〕本願において開
示される発明のうち代表的なものの概要を簡単に説明す
れば、下記のとおりである。[Means for solving the problems] A brief summary of typical inventions disclosed in this application is as follows.
すなわち、少なくともボンディングワイヤと接続する部
分の導電層の中央部の肉厚と縁部の肉厚をほぼ一定にな
るように形成することである。That is, at least the portion of the conductive layer connected to the bonding wire is formed so that the thickness of the center portion and the thickness of the edge portion are approximately constant.
上記した手段によれば、ボンディングワイヤを平坦な導
電層にボンディングできるので圧着面積を大にしてさら
に一様な荷重を加えられるので、導電層とボンディング
ワイヤの接合強度を向上させることができるものである
。According to the above-mentioned means, since the bonding wire can be bonded to the flat conductive layer, the crimping area can be increased and a more uniform load can be applied, so that the bonding strength between the conductive layer and the bonding wire can be improved. be.
〔実施例〕
第１図は本発明の一実施例であるセラミック封止の半導
体装置の概略図、第２図は第１図のＡ−Ａ線断面拡大図
である。[Embodiment] FIG. 1 is a schematic diagram of a ceramic-sealed semiconductor device according to an embodiment of the present invention, and FIG. 2 is an enlarged cross-sectional view taken along line A--A in FIG. 1.
なお、第１図のセラミック封止半導体装置と同一構成部
分については同一符号を付し、その説明は省略する。セ
ラミック基板１には導電層（例えば金等）１１の配線方
向に溝１２が形成されている。この溝１２には導電層１
１が、その縁部１３と中央部１４の肉厚がほぼ一定で、
かつセラミック基板１の表面と導電層１１の表面が平坦
となるように形成されている。Components that are the same as those of the ceramic-sealed semiconductor device shown in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted. A groove 12 is formed in the ceramic substrate 1 in the direction of wiring of a conductive layer (for example, gold, etc.) 11 . This groove 12 has a conductive layer 1
1, the wall thickness of the edge part 13 and the center part 14 is almost constant,
Further, the surface of the ceramic substrate 1 and the surface of the conductive layer 11 are formed to be flat.
次に第３Ａ図〜第３Ｆ図を用いて第１Ａ図のセラミック
封止半導体装置の製造プロセスの一例を示す。第３Ａ図
のようなセラミック基板１上に溝１２を導電層１１の配
線方向に形成したのち（第３Ｂ図）、前記溝１２に導電
層１１を形成する。Next, an example of the manufacturing process of the ceramic sealed semiconductor device shown in FIG. 1A will be described using FIGS. 3A to 3F. After forming grooves 12 in the wiring direction of the conductive layer 11 on the ceramic substrate 1 as shown in FIG. 3A (FIG. 3B), the conductive layer 11 is formed in the grooves 12.
このとき、導電層１１０表面縁部１３ａがセラミック基
板１の表面１ａと同じ高さ、あるいはそれ以上となるよ
うに形成する。そして、前記導電層１１をセラミック基
板１０表面１ａと一致するようにエツチング、研削、あ
るいはスタンピングして平坦になるようにする。At this time, the surface edge 13a of the conductive layer 110 is formed to be at the same height as or higher than the surface 1a of the ceramic substrate 1. Then, the conductive layer 11 is etched, ground, or stamped to be flat so as to match the surface 1a of the ceramic substrate 10.
すなわち、導電層１１の縁部１３と中央部１４の肉厚が
一定の厚さとなる（第３Ｄ図）。このセラミック基板１
に低融点ガラス１５ａを介してパッケージ−Ｆ部７を固
着する（第３Ｅ図）。その後、キャビティ２内に半導体
ベレット３を取り付け、ワイヤボンディングにより半導
体ペレット３上の電接と導電層１１とをボンディングワ
イヤ６にて接続する。このとき、第４図に示すように導
電層１１の表面縁部１３と中央部１４が平坦となってい
るので表面縁部１３に丸味のない分だけボンディングワ
イヤ６のヘッド部６ａとの接着面積を大きくとれ、かつ
、一様な荷重圧でヘッド部６ａを導電層に抑圧できるの
で接合強度を第６図に示した場合に比べ増大できるとい
う効果が得られる。That is, the thickness of the edge portion 13 and the center portion 14 of the conductive layer 11 becomes constant (FIG. 3D). This ceramic substrate 1
The package F part 7 is fixed to the package through the low melting point glass 15a (FIG. 3E). Thereafter, the semiconductor pellet 3 is installed in the cavity 2, and the electrical connection on the semiconductor pellet 3 and the conductive layer 11 are connected by a bonding wire 6 by wire bonding. At this time, since the surface edge 13 and center portion 14 of the conductive layer 11 are flat as shown in FIG. Since the head portion 6a can be suppressed by the conductive layer with a uniform load pressure, the bonding strength can be increased compared to the case shown in FIG. 6.
従って、前述した実施例においては、下記に示すような
作用効果を有する。Therefore, the above embodiment has the following effects.
ｍ 導電層の縁部の厚さが、少なくともボンディング
ワイヤとの接合部分において、導電層の中央部とほぼ同
じ厚さにすることにより、少なくともボンディング点で
は導電層か平坦となるので、ボンディングワイヤとの接
合面積を大にでき、ボンディング接合強度を向上できる
という効果が得られる。m By making the thickness of the edge of the conductive layer, at least at the part where it joins the bonding wire, approximately the same thickness as the center of the conductive layer, the conductive layer becomes flat at least at the bonding point, so that it is easy to connect with the bonding wire. This has the effect that the bonding area can be increased and the bonding strength can be improved.
（２）導電層の縁部の厚さが、少なくともボンディング
ワイヤとの接合部分において、導電層の中央部とほぼ同
じ厚さにすることにより、少なくともボンディング点で
は導電層が平坦となるので、ボンディング荷重を一様な
分布で加えられるので、ボンディング接合強度を向上で
きるという効果が得られる。(2) By making the thickness of the edge of the conductive layer, at least at the part where it joins the bonding wire, approximately the same thickness as the center of the conductive layer, the conductive layer becomes flat at least at the bonding point, so that bonding Since the load can be applied in a uniform distribution, it is possible to improve the bonding strength.
（３）導電層の表面と底面の幅をほぼ一定に形成するこ
とにより、リード数が増大したときにボンディングに必
要な導電層の幅を得るために、表面の縁部の丸味分を考
慮して底面の幅をかなり大きくとる必要がなく、導電層
の細線化、すなわちリード数の増大に対応が容易となる
効果が得られる。(3) By forming the width of the top and bottom surfaces of the conductive layer to be approximately constant, the roundness of the edges of the surface is taken into consideration in order to obtain the width of the conductive layer necessary for bonding when the number of leads increases. Therefore, it is not necessary to make the width of the bottom surface considerably large, and it is possible to easily respond to thinning of the conductive layer, that is, an increase in the number of leads.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。たとえば、溝を形成す
ることなく、セラミック基板表面に、縁部と中央部の肉
厚かはぼ同じ導電層を形成しても良い。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, a conductive layer may be formed on the surface of a ceramic substrate with approximately the same thickness at the edges and at the center without forming a groove.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である半導体装置に適用し
た場合についてｂ９明したが、それに限定されるもので
はなく、たとえば、プリント基板に配線として導電層を
形成する場合にも適用することができるものである。The above explanation has mainly focused on the case where the invention made by the present inventor is applied to semiconductor devices, which is the background field of application, but the invention is not limited thereto. It can also be applied when forming layers.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、少なくともボンディングワイヤと接続する導
電層の表面の縁部の丸味をなくし平坦にすることにより
、ボンディングワイヤと導電層との接合面積を大にして
接合強度を向上できるという効果が得られる。That is, at least by eliminating the roundness of the edge of the surface of the conductive layer connected to the bonding wire and making it flat, it is possible to increase the bonding area between the bonding wire and the conductive layer and improve the bonding strength.
第１図は、本発明の一実施例であるセラミック封止の半
導体装置、
第２図は、第１図のＡ−Ａ線断面図、
（力
第３Ａ図〜第３Ｆ図は第１図の半導体装置の製造方法説
明図、
第４図は本実施例のワイヤボンディングワイヤ周辺を示
す拡大断面図、
第５図は従来のセラミック封止の半導体装置の構成図、
第６図は従来の問題点を説明するための図である。
１・・・セラミック基板、２・・・キャビティ、３・・
・半導体ペレット、４・・・リード、５，１１・・・導
電体、６・・・ボンディングワイヤ、６ａ・・・ボンデ
ィングヘッド、７・・・パッケージ上部、８，１５・・
・低融点ガラス、９・・・蓋、１２・・・溝、１３・・
・縁部、１４・・・中央部。
第３７：図
ノｓｂ
第 ５ 図
第 ４ 図
第 ６ 図FIG. 1 is a ceramic-sealed semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line A-A in FIG. An explanatory diagram of a method for manufacturing a semiconductor device. FIG. 4 is an enlarged sectional view showing the vicinity of the wire bonding wire of this embodiment. FIG. 5 is a configuration diagram of a conventional ceramic-sealed semiconductor device. FIG. 6 is a problem with the conventional method. It is a diagram for explaining. 1... Ceramic substrate, 2... Cavity, 3...
- Semiconductor pellet, 4... Lead, 5, 11... Conductor, 6... Bonding wire, 6a... Bonding head, 7... Upper part of package, 8, 15...
・Low melting point glass, 9...lid, 12...groove, 13...
-Edge, 14...Central part. Figure 37: Figure sb Figure 5 Figure 4 Figure 6
Claims (1)
ヤと、外部端子とを電気的に接続するために、絶縁基板
上に導電層が形成されている半導体装置において、導電
層の縁部の厚さが、少なくともボンディングワイヤとの
接合部分において、導電層の中央部とほぼ同じ厚さであ
ることを特徴とする半導体装置。1. In a semiconductor device in which a conductive layer is formed on an insulating substrate in order to electrically connect the bonding wire connected to the electrode on the pellet and an external terminal, the thickness of the edge of the conductive layer has approximately the same thickness as the central portion of the conductive layer, at least in the bonding portion with the bonding wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61035158A JPS62195158A (en) | 1986-02-21 | 1986-02-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61035158A JPS62195158A (en) | 1986-02-21 | 1986-02-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62195158A true JPS62195158A (en) | 1987-08-27 |
Family
ID=12434073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61035158A Pending JPS62195158A (en) | 1986-02-21 | 1986-02-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62195158A (en) |
-
1986
- 1986-02-21 JP JP61035158A patent/JPS62195158A/en active Pending
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