JPS62194682A - Manufacture of pin diode - Google Patents
Manufacture of pin diodeInfo
- Publication number
- JPS62194682A JPS62194682A JP3699286A JP3699286A JPS62194682A JP S62194682 A JPS62194682 A JP S62194682A JP 3699286 A JP3699286 A JP 3699286A JP 3699286 A JP3699286 A JP 3699286A JP S62194682 A JPS62194682 A JP S62194682A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resistance
- low resistance
- prescribed
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 4
- 238000010438 heat treatment Methods 0.000 claims abstract 2
- 238000005498 polishing Methods 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 8
- 150000004767 nitrides Chemical class 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract 1
- 229910052796 boron Inorganic materials 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 3
- 239000000969 carrier Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は超高周波帯で使用されるＰＩＮダイオードの製
造方法に関し、特にＡＧＣスイッチ等に用いるＰＩＮダ
イオードのチップの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a PIN diode used in an ultra-high frequency band, and particularly to a method of manufacturing a PIN diode chip used in an AGC switch or the like.
Ｐ Ｉ Ｎダイオードは真性に近い高比抵抗半導体によ
って分離された高濃度にドープされたｎ領域とｎ領域を
有した構造をもっている１、超高周波帯において、順方
向バイアスの場き、この真性に近い高比抵抗層（以下ｉ
層と呼ぶ）に両速濃度層からそれぞれにキャリアが注入
され非常に低いインピーダンスを示し、又逆方向バイア
スの場合は非常に高いインピーダンスをもっていること
、又ｉ層によってきまる高周波抵抗がダイオードのバイ
アスの変化によって連続的に変化することを利用した乙
のである。このバイアス電流対高周波抵抗の関係は下の
式によって表わされる。A P I N diode has a structure with a highly doped n region and an n region separated by a high resistivity semiconductor close to the intrinsic property.1 In the ultra-high frequency band, when forward biased, this intrinsic Near high resistivity layer (hereinafter referred to as i
carriers are injected from the bi-velocity concentration layer into the two layers (called "layer"), which exhibits a very low impedance, and in the case of reverse bias, it has a very high impedance, and the high frequency resistance determined by the i-layer is due to the bias of the diode. It is a method that takes advantage of the fact that it changes continuously due to changes. The relationship between bias current and high frequency resistance is expressed by the equation below.
Ｒｄ”Ｗ２．−’μτ■。Rd”W2.−’μτ■.
ここでＲｄは高周波抵抗、Ｗは高濃度９層およびｎ層を
分離する距離、すなわちｉ層の厚さ、１ｔ 。Here, Rd is the high frequency resistance, W is the distance separating the high concentration 9 layers and the n layer, that is, the thickness of the i layer, and 1t.
ではそれぞれキャリアの移動度およびライフタタイム、
■・は印加電流である。すなわち、ＰＩＮダイオードの
主特性はｉ層の厚さによって決定され、通常種々の目的
に応じて数１ｔ ｒｎから２００μｍの範囲のものが主
流となっている。The carrier mobility and lifeta time, respectively, are
■・ is the applied current. That is, the main characteristics of a PIN diode are determined by the thickness of the i-layer, which is usually in the range of several 1 trn to 200 μm depending on various purposes.
従来、この種のＰＩＮダイオードは低抵抗シリコン基板
にエピタキシャル成長によって所定のｉ層を形成し、こ
のｉ層に低抵抗基板と逆の導電型を有する低抵抗層を拡
散等の手法によって形成して、いたり、又真性に近い高
比抵抗シリコン基板を研磨及びエツチングによって所定
の厚さにした後、両面にそれぞれ別の導電型の低抵抗層
を拡散等によって形成したちのである。通常ｉ層が１０
０ Ｂｍ以下のものはエピタキシャル層分、１００〜２
００μｍのものは基板を利用したものが主流である。Conventionally, this type of PIN diode is made by forming a predetermined i-layer on a low-resistance silicon substrate by epitaxial growth, and forming a low-resistance layer having a conductivity type opposite to that of the low-resistance substrate on this i-layer by a method such as diffusion. Alternatively, after polishing and etching a near-intrinsic high-resistivity silicon substrate to a predetermined thickness, low-resistance layers of different conductivity types are formed on both surfaces by diffusion or the like. Usually the i layer is 10
For those below 0 Bm, the epitaxial layer is 100 to 2
The mainstream of 00 μm ones is those using a substrate.
［発明が解決しようとする問題点〕
上述した従来のＰＩＮダイオードの製法のうち、高抵抗
エピタキシャル層をｉ層として利用する方法は、このｉ
層の結晶性及び抵抗率の点で高抵抗基板を利用したもの
にくらべ劣り、高周波特性において、特にバイアスのオ
ン、オフ時の高周波抵抗比が小さい（誠穴’ｆ：：’ｆ
、Ａ （Ｉｉ （、”、の場合ダイナミック側５ンジが
小さい、スイ・ソチの場合アイソレーションが小さい）
′８の欠点がある。ｙ、】層として高比抵抗シリコン基
板を利用した場き、近年比〃（抗が１００Ω（・ｍ以−
ヒという良好な結晶が容易に得られるようになっている
。しかし１ンの特性の要求からｉ層の厚さは２００ μ
ｍ以下（２００μｍ以上の場き一般にバイアスのオン時
の抵抗を下げるために数百ｍ Ａという大電流が必要で
実用的でない）が要求されるためＰＩＮダイオ−トチ・
ツブの製造中にウェーハが割れやすく、量産性に劣ると
いう欠点を有していた。[Problems to be Solved by the Invention] Among the conventional PIN diode manufacturing methods described above, the method of using a high-resistance epitaxial layer as the i-layer is
In terms of crystallinity and resistivity of the layer, it is inferior to that using a high-resistance substrate, and in terms of high-frequency characteristics, the high-frequency resistance ratio is small, especially when the bias is on and off.
,A (Ii (,'', the dynamic side is small, the isolation is small in the case of Sui-Sochi)
There are 8 drawbacks. When using a high-resistivity silicon substrate as a layer, compared to recent years, the resistance is 100Ω (・m or more).
It is now possible to easily obtain good crystals. However, due to the requirements for the characteristics of 1, the thickness of the i layer is 200 μm.
(If the diameter is 200 μm or more, a large current of several hundred mA is required to lower the resistance when the bias is turned on, which is impractical.)
This method had the disadvantage that the wafers were easily broken during the manufacture of the tubes, and mass productivity was poor.
本発明の目的は高周波特性が優れ、しかもウェーハの割
れ等の量産性の問題ら解決されたＰＩＮダイオードの製
造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a PIN diode which has excellent high frequency characteristics and which solves mass production problems such as cracking of wafers.
〔問題点を解決するための手段Ｊ
本発明のＰＩＮダイオードの製造方法は、通常取扱い上
問題のない厚さの高比抵抗シリコン基板の一面に所定の
大きさを有する低抵抗層を拡散等の手段を用いて形成し
、前記シリコン基板を研磨エツチング等によって所定の
厚さに仕上げた後、前記低抵抗層と逆の導電型をもった
不純物をドープした多結晶シリコンを１００〜１５０μ
ｍ程度成長することにより構成される。[Means for Solving the Problems J] The method for manufacturing a PIN diode of the present invention involves depositing a low-resistance layer of a predetermined size on one surface of a high-resistivity silicon substrate with a thickness that does not pose problems in normal handling, such as by diffusion. After finishing the silicon substrate to a predetermined thickness by polishing and etching, etc., a layer of polycrystalline silicon doped with an impurity having a conductivity type opposite to that of the low resistance layer is deposited to a thickness of 100 to 150 μm.
It is formed by growing about m.
次に、本発明の実施例について図面を参照して説明する
。第１図（ａ）〜（ｄ）は本発明の一実施例を説明する
ために工程順に示したチップの断面図である。以下、工
程順に本°発明の一実施例を説明する。Next, embodiments of the present invention will be described with reference to the drawings. FIGS. 1(a) to 1(d) are cross-sectional views of a chip shown in the order of steps for explaining an embodiment of the present invention. An embodiment of the present invention will be described below in order of steps.
まず、第１図（ａ）に示すように、１００Ω１以上とい
う高比抵抗ｎ型シリコン基板１の所定の厚さのシリコン
酸化膜２に所定の大きさの窓を形成しホウ素拡散等によ
ってｎ型低抵抗層３を形成したのち全面にシリコン酸化
膜、又は窒化膜４等を形成する。First, as shown in FIG. 1(a), a window of a predetermined size is formed in a silicon oxide film 2 of a predetermined thickness on an n-type silicon substrate 1 with a high specific resistance of 100Ω1 or more, and an n-type After forming the low resistance layer 3, a silicon oxide film, a nitride film 4, etc. is formed on the entire surface.
次に、第１図（ｂ）に示すように、その後上記高抵抗基
板１を研磨、エツチング等の手段によっテ目的ノＲｄ特
性を得る厚さく ５０ＭＩＩｚ 〜ｌ０ＧＨｚ に’）
減衰器、ＡＧＣ、スイッチの場合１００〜１５０μｍ程
度）にしたのち、Ａｓ等をドープした低抵抗の多結晶シ
リコン５を１００〜１５０μｍ程度形成する。Next, as shown in FIG. 1(b), the high-resistance substrate 1 is polished to a thickness of 50 MIIz to 10 GHz to obtain the desired Rd characteristics by means such as polishing and etching.
(in the case of attenuators, AGCs, and switches, the thickness is about 100 to 150 μm), and then a low-resistance polycrystalline silicon 5 doped with As or the like is formed to a thickness of about 100 to 150 μm.
次に、第１図（ｃ）に示すように、多結晶シリコン５を
形成したウェーハを熱処理することによってｎ型低抵抗
層６を形成する。Next, as shown in FIG. 1(c), the wafer on which the polycrystalline silicon 5 has been formed is heat treated to form an n-type low resistance layer 6.
次に、第１図（ｄ）に示すように、ρ型紙抵抗層３上の
シリコン酸化膜、窒化膜等に窓７を形成し、所定の金属
によって電Ｉｉ８を形成する。Next, as shown in FIG. 1(d), a window 7 is formed in the silicon oxide film, nitride film, etc. on the ρ-shaped paper resistance layer 3, and an electrode Ii8 is formed of a predetermined metal.
以、Ｅにより本実施例は完成する。Hereinafter, this embodiment is completed by E.
以上説明したように、本発明はＰＩＮダイオードのｉ層
に高抵抗基板を使用することによって良好な高周波特性
を得ることが出来、従来の欠点であったウェーハ割れ等
の量産性の問題も低抵抗多結晶シリコンを上記高比抵抗
を薄くしたすぐ後に形成することによって改善すること
が出来る。As explained above, the present invention can obtain good high-frequency characteristics by using a high-resistance substrate for the i-layer of the PIN diode. This can be improved by forming polycrystalline silicon immediately after thinning the high resistivity.
第１図（ａ）〜・（（１）は本発明の一実施例を説明す
るために工程順に示したチップの１断面図である。
］・・・高比抵抗シリコン基板、２・・・シリコン酸化
膜、３・・・ｎ型低抵抗拡散層、４・・・シリコン酸化
膜又は窒化膜、５・・・＾Ｓドープ多結晶シリコン、６
・・・ｎ型低抵抗拡散層、７・・・電極用の窓、８・・
・金属電極。FIGS. 1(a) to 1((1) are cross-sectional views of a chip shown in the order of steps for explaining an embodiment of the present invention.) High resistivity silicon substrate, 2... Silicon oxide film, 3... N-type low resistance diffusion layer, 4... Silicon oxide film or nitride film, 5...^S-doped polycrystalline silicon, 6
... n-type low resistance diffusion layer, 7... window for electrode, 8...
・Metal electrode.
Claims (1)
さを有する低抵抗層を拡散等の手段をもちいて形成し、
上記シリコン基板を研磨エッチング等の手段をもちいて
所定の厚さに仕上げた後、前記低抵抗層と逆の導電型を
有する低抵抗多結晶シリコンを形成し、熱処理をしたの
ち両低抵抗層に所定の金属によって電極を形成すること
を特徴としたＰＩＮダイオードの製造方法。A low resistance layer having a predetermined size is formed on one surface of a high resistivity silicon substrate having a predetermined thickness by using means such as diffusion,
After finishing the silicon substrate to a predetermined thickness using polishing etching or other means, low-resistance polycrystalline silicon having a conductivity type opposite to that of the low-resistance layer is formed, and after heat treatment, both low-resistance layers are A method for manufacturing a PIN diode, characterized in that an electrode is formed of a predetermined metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3699286A JPS62194682A (en) | 1986-02-20 | 1986-02-20 | Manufacture of pin diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3699286A JPS62194682A (en) | 1986-02-20 | 1986-02-20 | Manufacture of pin diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62194682A true JPS62194682A (en) | 1987-08-27 |
Family
ID=12485236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3699286A Pending JPS62194682A (en) | 1986-02-20 | 1986-02-20 | Manufacture of pin diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62194682A (en) |
-
1986
- 1986-02-20 JP JP3699286A patent/JPS62194682A/en active Pending
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