JPS62191908A - Power consumption reducing circuit for electronic circuit - Google Patents

Abstract

PURPOSE:To minimize the average power consumption by changing a clock speed so as to vary an action speed. CONSTITUTION:The titled circuit is comprised of a variable speed clock generation part 1 to generate a variable speed clock signal 2, and a control part 3 composed of elements such as a CMOS to generate a clock speed control signal 4, which controls the variable speed clock generation part 1 in synchronization with the variable speed clock 2 according to a preset program, to said part 1. If a request to modify the clock speed is issued to the interior of the control part 3, it outputs the clock speed control signal 4 corresponding to the request to the variable speed clock generation part 1. It generates the variable speed clock signal 2 based on the control signal 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power consumption reduction circuit for electronic circuits that aims to reduce the average power consumption of electronic circuits such as electronic control means.

[Conventional technology]

Examples of conventional electronic circuits that aim to reduce power consumption include:
There is one shown in Figure 4. This electronic circuit is powered by a power supply (+5v
) supply Vcc terminal, C to which a constant clock signal is applied
It has a microprocessor 40 such as 0MO3 having an LK terminal and an INT terminal into which an interrupt signal is input,
It has an active mode and a sleeve mode as its operating modes, and when the sleeve mode is selected, the average power consumption is reduced (for example, Hitachi Microcomputer Data Book, 8-bit 16-Bit Multichip, September 1980 ■Published by Hitachi, p. 101).

In the above configuration, the microprocessor 40 is in either the active mode, which is a normal state, or the sleep mode, which reduces power consumption. If you execute a sleeve command while in active mode, it will transition to sleeve mode. Furthermore, if an interrupt input (applied to the NT terminal) occurs during the sleeve mode, the mode shifts to the active mode. In sleep mode, average power consumption is reduced to a fraction of that in active mode, but
All functions other than interrupt reception are stopped. Such a sleeve mode is effective when the amount of power that can be supplied is limited, such as when the power source is a battery. Equipment with such a need include hand belt computers, hand belt printer plotters, and the like.

When the microprocessor 40 shown in FIG.
(e.g., memory, input/output devices).

When data, paper feeding commands, etc. are input to the printer plotter from the outside, the microprocessor 40 executes print plotting, paper feeding, etc. (these processes require high speed). On the other hand, when there is no external human power, the microprocessor 40 executes processing to poll various sensors for detecting the presence or absence of external input and abnormalities such as paper jams. This process may be performed at a low speed, whereas the above-mentioned processing requires high speed.

Therefore, the microprocessor 40 can reduce the average power consumption by placing the microprocessor 40 in the active mode for only a single period at predetermined time intervals and in the sleep mode for the other periods (which account for most of the time). To change from sleeve mode to active mode, an interrupt signal is required, but it is necessary to generate an interrupt signal periodically using an interval timer, or to receive commands from the outside, ○R output of abnormal outputs from various sensors, etc. This can be achieved by using .

[Problem that the invention seeks to solve]

However, in the conventional power consumption reduction means, since a constant speed clock is used even in the sleep mode, there is a problem in that there is a limit to the reduction of average power consumption.

Furthermore, since interrupts are used to change modes, not only does one of the valuable interrupt pins have to be dedicated to mode switching, but in peripheral circuits, a single signal is required to switch to active mode. There is an inconvenience that various circuits must be provided for grouping into lines.

[Means to solve the problem]

The present invention has been made in view of the above, and provides a power consumption reduction circuit for electronic circuits that can change the operating speed by changing the clock speed in order to reduce the average power consumption to the limit. It is something.

[Effect]

According to the power consumption reduction circuit for an electronic circuit of the present invention, for example, by lowering the clock speed when the processing load is low, the operating speed is slowed down, and the average power consumption is further reduced than before.

〔Example〕

Hereinafter, the power consumption reduction circuit for electronic circuits according to the present invention will be explained in detail.

FIG. 1 shows an embodiment of the present invention, in which a variable speed clock generator 1 generates a variable speed clock signal 2, and a variable speed clock generator 1 according to a preset program in synchronization with the variable speed clock 2. The CMO 3 outputs a clock speed control signal 4 to the variable speed clock generator 1 to control the clock speed control signal 4.
The control section 3 is constructed using elements such as the following.

In the above configuration, when a request to change the clock speed is issued within the control section 3, the control section 3 outputs a clock speed control signal 4 corresponding to the request to the variable speed clock generation section 1. A variable speed clock generator 1 generates a variable speed clock signal 2 based on a control signal 4.

FIG. 2 shows details of the embodiment shown in FIG. 1, in which the variable speed clock generating section 1 includes a period register 5 that generates period designation data 6 according to data and commands given from the control section 3, and a period designation data 6. 6, a down counter 7 that generates a ripple carry output signal based on the constant clock signal 9, etc., and a constant clock oscillator 8 that generates the constant clock 9.
and a T-type flip-flop 11 that generates a variable speed clock signal 2 based on the ripple carry output signal 10.

Further, the control unit 3 controls the write data 13, the write address 15, and the write command 16 based on the variable speed clock signal 2.
microprocessor 12 that outputs , and write address 1
5 and a write command 16, an address decoder 14 outputs a write command 17 to the period register 5.
It consists of

In the configuration shown in FIG. 2, a period designating data clock is output from the period register 5 and inputted to the down counter 7 as data.

A constant clock signal 9 is input to the downcarrant, and a ripple carry output signal 10 is generated based on both inputs. This ripple carry output signal 10 is input to the CLK terminal of the flip-flop 11 and also to the LOAD terminal of the down counter 7.

A variable speed clock signal 2 is outputted to the Q terminal of the flip-flop 11 and inputted to the CLK terminal of the microprocessor 12 as a clock.

The microprocessor 12 operates in accordance with a program stored in memory in synchronization with the variable speed clock signal 2. When writing to the period register 5, the microprocessor 12 outputs a write address 15 and a command 16 to the address decoder 14.

Address decoder 14 outputs write command 17 to period register 5 as a clock. Upon input of this command 17, the period register 5 latches the write data 13. The latched data value is
Each time the down counter 7 outputs the pull carry signal 10, it is loaded into the down counter. The ripple carry output signal 10 output from the down counter 7 is a value obtained by dividing the constant clock signal 9 by the write data 13. This signal 10 is frequency-divided by two by a flip-flop 11 and then outputted to the microprocessor 12 as a variable speed clock signal 2. In this way, by changing the count number of the down counter 7, the clock cycle is changed, and the clock speed is changed.

FIG. 3 shows an embodiment of the invention, in which the clock selection signal 21
an amplifier down (U/D) counter 20 that generates constant clock signals 23a, 23b of different speeds, constant clock oscillators 21a, 21b, 21c that generate constant clock signals 23a, 23b of different speeds, and constant clock signals 23a to 23 based on the clock selection signal 21.
A variable speed clock generating section 1 is constituted by a multiplexer 24 that selects one of the clock signals C and outputs it as the variable clock signal 2.

Further, the control unit 3 forms a state machine together with the ROM 27, and uses the variable speed clock signal 2 as a clock to operate the ROM.
A status register 25 that generates a next address 26 and outputs an up/down clock signal 26 and an up/down designation signal 27 based on ROM read data 28
and a ROM 27 that outputs ROM read data 28 corresponding to the ROM netast address 26.

In the configuration shown in FIG. 3, based on the ROM next address 26 output from the status register 25, the corresponding read data 28 is output from the ROM 27. Up/down 1 determination signal 27 that specifies up or down for the U/D counter 20 by this read data 28
Output. Based on the up/down designation signal 27, the U/D counter 20 outputs a clock selection signal 21 to the multiplexer 24 for amplifying or downgrading the constant clock signal from the current value. Multiplexer 24 selects signal 2
1, one of the constant clocks 23a to 23c is selected and outputted to the control section 3 as a variable speed clock signal.

In the above embodiment, CMO3 is used, but the present invention is not limited to this, and NMO3, TTL, etc. can be used.

Further, although the case is shown in which one variable speed clock signal 2 is inputted to the control section, it is also possible to use two, for example, to provide a two-phase clock.

Furthermore, the clock speed can be delayed to a limit that guarantees normal operation, depending on environmental temperature, power supply voltage fluctuations, external noise level fluctuations, individual variations in the applied equipment, changes over time, etc. .

〔Effect of the invention〕

As explained above, according to the power consumption reduction circuit for electronic circuits of the present invention, since the clock speed can be changed, the average power consumption can be significantly reduced. Particularly, remarkable effects can be obtained when the control section is constituted by a CMO3 circuit. Furthermore, by applying the present invention to a microprocessor, clock control can be performed according to processing conditions and the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the invention, FIG. 2 is a detailed block diagram showing a specific embodiment of the invention, and FIG. 3 is a detailed block diagram showing another specific embodiment of the invention. , 4th
The figure is a circuit diagram showing an example of a circuit equipped with conventional power consumption reduction means. Explanation of symbols

Claims (1)

[Claims] A control unit that operates in synchronization with a clock signal and outputs a control signal that reduces the clock speed; and a control unit that receives the control signal of the control unit and generates a clock signal that reduces the speed. A power consumption reduction circuit for an electronic circuit, characterized by comprising a variable speed clock generator.