JPS62190721A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62190721A JPS62190721A JP3236086A JP3236086A JPS62190721A JP S62190721 A JPS62190721 A JP S62190721A JP 3236086 A JP3236086 A JP 3236086A JP 3236086 A JP3236086 A JP 3236086A JP S62190721 A JPS62190721 A JP S62190721A
- Authority
- JP
- Japan
- Prior art keywords
- silicide
- impurity
- substrate
- single crystal
- grains
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000012535 impurity Substances 0.000 claims abstract description 35
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 30
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 29
- 238000009792 diffusion process Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000013078 crystal Substances 0.000 claims abstract description 6
- 238000002844 melting Methods 0.000 claims abstract 2
- 230000008018 melting Effects 0.000 claims abstract 2
- 239000002184 metal Substances 0.000 claims abstract 2
- 238000010438 heat treatment Methods 0.000 claims description 6
- 230000007547 defect Effects 0.000 abstract description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 7
- 239000011574 phosphorus Substances 0.000 abstract description 7
- 239000010409 thin film Substances 0.000 abstract description 3
- 125000004437 phosphorous atom Chemical group 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置製造における、半導体単結晶基板
への不純物拡散方法に関する0特に浅い接合を持つ不純
物拡散層の形成において有効である。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for diffusing impurities into a semiconductor single crystal substrate in semiconductor device manufacturing, and is particularly effective in forming an impurity diffusion layer having a shallow junction.
本発明の半導体装置の製造方法は、拡散層を形成すべき
領域に高濃度不純物を含んだアモルファスまたは多結晶
シリサイドを形成後、熱処理を行ない該シリサイドのク
レーンを成長させることにより、該高濃度不純物を該半
導体基板中へ拡散させることを特徴とする。該シリサイ
ド上にP2O層を形成した後、シリサイド中の不純物を
拡散させる熱処理を行なえば、不純物の蒸発を抑制し・
より効率的な不純物の該半導体基板中への拡散を行なう
ことができる。In the method for manufacturing a semiconductor device of the present invention, after forming amorphous or polycrystalline silicide containing a high concentration impurity in a region where a diffusion layer is to be formed, heat treatment is performed to grow a crane of the silicide, thereby removing the high concentration impurity. is characterized by diffusing into the semiconductor substrate. After forming the P2O layer on the silicide, if heat treatment is performed to diffuse the impurities in the silicide, evaporation of the impurities can be suppressed.
Impurities can be more efficiently diffused into the semiconductor substrate.
従来の半導体装置製造方法による不純物拡散層の形成は
、J、Electrochem、Soc、1145’V
o1131.陽5.(1984)に示されるように、イ
オン打込みにより不純物を半導体基板中に直接注入後、
アニーリングを行なうことによりなされていた。Formation of an impurity diffusion layer by a conventional semiconductor device manufacturing method is described in J, Electrochem, Soc, 1145'V
o1131. Yang 5. (1984), after directly implanting impurities into the semiconductor substrate by ion implantation,
This was done by performing annealing.
しかしながら、半導体基板中に不純物イオンを直接注入
した場合、欠陥が生じ、了ニー゛リングにより不純物を
活性化する時、欠陥にょる増速拡散が500x程度生じ
浅い接合を持つ不純物拡散層の形成を困難にする。また
イオン注入による欠陥は、了ニーリング処理で完全には
結晶性が回復しないため微少リークが接合で生じるとい
う問題があった・本発明の目的とするところは、かがる
従来技術の問題点を取り除き、イオン注入のため生じる
欠陥の生じない、しがも浅い接合形成を可能にする不純
物拡散の製造方法を与えることである。However, when impurity ions are directly implanted into a semiconductor substrate, defects occur, and when the impurities are activated by kneeling, accelerated diffusion due to defects occurs by about 500x, making it difficult to form an impurity diffusion layer with a shallow junction. make it difficult In addition, defects caused by ion implantation have a problem in that the crystallinity cannot be completely recovered by the annealing treatment, resulting in slight leakage in the bonding.The purpose of the present invention is to solve the problems of the conventional technology It is an object of the present invention to provide a manufacturing method for impurity diffusion that does not cause defects caused by ion implantation and yet enables the formation of shallow junctions.
問題点を解決するためイオン注入は行なわず、拡散源と
なるシリサイド層をOVDまたはスパッタリングにより
、シリサイドに不純物を含ませて蓄積し、熱処理により
シリサイドのグレインを成長させることによりグレイン
境界中に存在する不純物を掃き出させ、半導体基板中に
不純物を拡散させる。従って、半導体単結晶中には欠陥
が生じない・また熱拡散は半導体基板中で拡散係数の小
さい領域でかつシリサイドのグレインが成長する湿度と
時間を選ぶことにより、高濃度の浅い不純物拡散層の形
成が可能になる・本発明の作用を述べれば、半導体基板
上に形成された不純物を含むシリサイドは拡散源の役割
を果す。また該シリサイド後の熱処理は半導体基板中で
不純物の拡散が最小でかつ、該シリサイドのグレインを
成長させる条件を満たす温度と時間で行なうことにより
浅い接合の形成が可能になる。To solve this problem, ion implantation is not performed, but the silicide layer that serves as a diffusion source is impurity-filled and accumulated in the silicide by OVD or sputtering, and the silicide grains are grown by heat treatment to form silicide grains that exist in the grain boundaries. The impurities are swept out and diffused into the semiconductor substrate. Therefore, no defects occur in the semiconductor single crystal.Thermal diffusion is achieved by selecting a region with a small diffusion coefficient in the semiconductor substrate and the humidity and time in which silicide grains grow, forming a highly concentrated shallow impurity diffusion layer. Describing the function of the present invention, silicide containing impurities formed on a semiconductor substrate serves as a diffusion source. In addition, by performing the post-silicide heat treatment at a temperature and time that minimizes the diffusion of impurities in the semiconductor substrate and satisfies the conditions for growing the silicide grains, it becomes possible to form a shallow junction.
本発明の作用を述べれば、不純物を含むシリサイドを拡
散源に用いた熱拡散により半導体基板中に不純物拡散す
るため、イオン打込による欠陥の発生が生じない。また
不純物拡散は、シリサイドのグレインが成長することに
より行なわれるため、半導体基板中の拡散係数がシリサ
イド中の拡散係数よりも非常に小さい理由から、半導体
基板中には高濃度かつ浅い不純物の分布を形成すること
ができる。To describe the effect of the present invention, since impurities are diffused into the semiconductor substrate by thermal diffusion using silicide containing impurities as a diffusion source, defects caused by ion implantation do not occur. In addition, since impurity diffusion is performed by the growth of silicide grains, the diffusion coefficient in the semiconductor substrate is much smaller than that in silicide, so a high concentration and shallow impurity distribution is required in the semiconductor substrate. can be formed.
以下ひとつの実施例を説明する。 One embodiment will be described below.
第1図において、単結晶シリコン基板1上には、リンを
含んだWシリサイド薄膜2が形成されている・次に基板
を約1050℃ 10sec単時間熱処理を行なうと、
Wシリサイドのグレイン成長に伴ない、リンネ細物がグ
レイン境界を通して高速で拡散し単結晶シリコン表面に
高濃度で分布する・この表面に蓄積された不純物のリン
原子は、1050℃、10(6)で単結晶シリコン中に
わずかに拡がり、高濃度リンの浅い拡散層4を形成する
。In FIG. 1, a W silicide thin film 2 containing phosphorus is formed on a single-crystal silicon substrate 1. Next, the substrate is heat-treated at approximately 1050° C. for 10 seconds, resulting in
As the grains of W silicide grow, Linnean particles diffuse at high speed through the grain boundaries and are distributed at high concentration on the single crystal silicon surface.The impurity phosphorus atoms accumulated on this surface are at 1050℃ and 10(6) Then, it spreads slightly into the single crystal silicon, forming a shallow diffusion layer 4 of highly concentrated phosphorus.
第2図は1050℃、10 sea熱処理後の基板を示
し、グレインの成長したWシリサイド3と単結晶シリコ
ン1中の浅い接合′を持つリン拡散層4からなる。FIG. 2 shows the substrate after heat treatment at 1050° C. and 10 seas, which consists of a W silicide 3 with grown grains and a phosphorus diffusion layer 4 with a shallow junction in single crystal silicon 1.
以上説明したように本発明によれば、欠陥の生じない浅
い不純物拡散の製造が可能になる。As explained above, according to the present invention, it is possible to manufacture a shallow impurity diffusion structure that does not cause defects.
第1図、第2図一本発明による浅い不純物拡散形成方法
の工程断面図。
1・・・単結晶シリコン基板
2・・・リンを含んだWシリサイド薄膜3・・・成長し
たグレインを持っWシリサイド4・・・浅いリンネ細物
拡散層
以 上FIGS. 1 and 2 are cross-sectional views showing the process of forming a shallow impurity diffusion method according to the present invention. 1... Single-crystal silicon substrate 2... W silicide thin film containing phosphorus 3... W silicide with grown grains 4... Shallow linne thin diffusion layer or more
Claims (1)
該単結晶基板上に不純物を含んだアモルファスまたはク
レーンの小さい多結晶高融点金属シリサイド層を低温に
て形成後、熱処理を行ない該シリサイドのクレーンを成
長させることにより、該不純物を該半導体基板へ拡散さ
せることを特徴とする半導体装置の製造方法。In a manufacturing method for impurity diffusion into a semiconductor single crystal substrate,
After forming an amorphous or small polycrystalline high melting point metal silicide layer containing impurities on the single crystal substrate at a low temperature, heat treatment is performed to grow the crane of the silicide, thereby diffusing the impurity into the semiconductor substrate. A method of manufacturing a semiconductor device, characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3236086A JPS62190721A (en) | 1986-02-17 | 1986-02-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3236086A JPS62190721A (en) | 1986-02-17 | 1986-02-17 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62190721A true JPS62190721A (en) | 1987-08-20 |
Family
ID=12356787
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3236086A Pending JPS62190721A (en) | 1986-02-17 | 1986-02-17 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62190721A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02216846A (en) * | 1988-03-30 | 1990-08-29 | American Teleph & Telegr Co <Att> | Manufacture of semiconductor device |
KR100612853B1 (en) * | 2004-07-21 | 2006-08-14 | 삼성전자주식회사 | Si based material layer having wire type silicide and method of forming the same |
-
1986
- 1986-02-17 JP JP3236086A patent/JPS62190721A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02216846A (en) * | 1988-03-30 | 1990-08-29 | American Teleph & Telegr Co <Att> | Manufacture of semiconductor device |
KR100612853B1 (en) * | 2004-07-21 | 2006-08-14 | 삼성전자주식회사 | Si based material layer having wire type silicide and method of forming the same |
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