JPS62190370U - - Google Patents
Info
- Publication number
- JPS62190370U JPS62190370U JP7827886U JP7827886U JPS62190370U JP S62190370 U JPS62190370 U JP S62190370U JP 7827886 U JP7827886 U JP 7827886U JP 7827886 U JP7827886 U JP 7827886U JP S62190370 U JPS62190370 U JP S62190370U
- Authority
- JP
- Japan
- Prior art keywords
- lead terminal
- board
- integrated circuit
- hybrid integrated
- mounting part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Landscapes
- Structure Of Printed Boards (AREA)
Description
第１図はこの考案の一実施例である厚膜集積回
路用基板の表側表面および裏側表面を示す部分平
面図、第２図はチエツクマーク間の相互距離の説
明図、第３図は許容限度を超えたリードパツドの
形成位置のずれが生じた場合の説明図、第４図は
この考案の変形例の説明図、第５図は従来の集積
回路用基板を用いた集積回路の製造工程図、第６
図は基板へのリード端子の取付説明図、第７図は
リードパツドの配置説明図、第８図はリード端子
の形状説明図、第９図および第１０図はリードパ
ツドの形成位置のずれの説明図である。
図において、１，２０は集積回路用基板、２は
膜パターン、４，４ａ，４ｂはリードパツド、１
０はスクライブ線、１１はリード端子、２１，２
５はチエツクマーク（位置指示マーク）、２３は
仮想スクライブ線を示す。なお、各図中同一符号
は同一または相当部分を示す。
Fig. 1 is a partial plan view showing the front and back surfaces of a thick film integrated circuit board that is an embodiment of this invention, Fig. 2 is an explanatory diagram of the mutual distance between check marks, and Fig. 3 is the tolerance limit. 4 is an explanatory diagram of a modification of this invention, and FIG. 5 is a diagram of the manufacturing process of an integrated circuit using a conventional integrated circuit substrate. 6th
The figure is an explanatory diagram of attaching the lead terminal to the board, Fig. 7 is an explanatory diagram of the arrangement of the lead pad, Fig. 8 is an explanatory diagram of the shape of the lead terminal, and Figs. 9 and 10 are explanatory diagrams of deviation in the formation position of the lead pad. It is. In the figure, 1 and 20 are integrated circuit substrates, 2 is a film pattern, 4, 4a, and 4b are lead pads, 1
0 is a scribe line, 11 is a lead terminal, 21,2
Reference numeral 5 indicates a check mark (position indicating mark), and reference numeral 23 indicates a virtual scribe line. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
に形成されてなるとともに、所定の切断線に沿つ
て切断されることによつて製品に応じた形状とな
る混成集積回路用基板であつて、 前記基板の表面のうち、前記リード端子取付部
の形成位置と所定の距離関係にある位置に位置指
示マークを設けたことを特徴とする混成集積回路
用基板。 (2) 基板は、その表側表面と裏側表面との双方
に膜パターンが形成された基板であり、 前記表側表面と裏側表面とのうち、リード端子
取付けの際の位置決め基準とされる表面の反対側
の表面に位置指示マークを設けたことを特徴とす
る、実用新案登録請求の範囲第１項記載の混成集
積回路用基板。 (3) 位置指示マークを、リード端子取付部の際
の位置決め基準とされる表面の反対側の表面にお
いて、リード端子取付部の形成位置を基準とした
場合に想定される仮想的切断線を中心として対で
設けるとともに、対とされた前記位置指示マーク
の間の相互距離を、前記リード端子取付部の形成
位置とリード端子の取付位置とのずれの許容最大
値に応じた距離としたことを特徴とする、実用新
案登録請求の範囲第２項記載の混成集積回路用基
板。[Claims for Utility Model Registration] (1) A hybrid product in which a film pattern including a lead terminal attachment part is formed on the surface and is cut along a predetermined cutting line to form a shape according to the product. 1. A hybrid integrated circuit board, characterized in that a position indicating mark is provided on the surface of the board at a position at a predetermined distance from the formation position of the lead terminal attachment part. (2) The board is a board on which a film pattern is formed on both the front surface and the back surface, and of the front surface and back surface, the opposite surface is used as a positioning reference when attaching the lead terminal. A board for a hybrid integrated circuit according to claim 1, characterized in that a position indicating mark is provided on the side surface. (3) Place the position indicator mark on the surface opposite to the surface that is used as the positioning reference for the lead terminal mounting part, centering it on the hypothetical cutting line that is assumed to be based on the formation position of the lead terminal mounting part. In addition, the mutual distance between the pair of position indication marks is determined according to the maximum allowable deviation between the formation position of the lead terminal mounting part and the mounting position of the lead terminal. A board for a hybrid integrated circuit according to claim 2 of the utility model registration claim.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986078278U JPH0623014Y2 (en) | 1986-05-23 | 1986-05-23 | Substrate for hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986078278U JPH0623014Y2 (en) | 1986-05-23 | 1986-05-23 | Substrate for hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62190370U true JPS62190370U (en) | 1987-12-03 |
| JPH0623014Y2 JPH0623014Y2 (en) | 1994-06-15 |
Family
ID=30927067
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986078278U Expired - Lifetime JPH0623014Y2 (en) | 1986-05-23 | 1986-05-23 | Substrate for hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0623014Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6068671U (en) * | 1983-10-17 | 1985-05-15 | 矢崎総業株式会社 | printed wiring board |
-
1986
- 1986-05-23 JP JP1986078278U patent/JPH0623014Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6068671U (en) * | 1983-10-17 | 1985-05-15 | 矢崎総業株式会社 | printed wiring board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0623014Y2 (en) | 1994-06-15 |