JPS62189804A - Detection and integration circuit - Google Patents
Detection and integration circuitInfo
- Publication number
- JPS62189804A JPS62189804A JP3233586A JP3233586A JPS62189804A JP S62189804 A JPS62189804 A JP S62189804A JP 3233586 A JP3233586 A JP 3233586A JP 3233586 A JP3233586 A JP 3233586A JP S62189804 A JPS62189804 A JP S62189804A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- amplifier
- inverting
- detection
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 title claims abstract description 42
- 230000010354 integration Effects 0.000 title claims abstract description 19
- 238000006243 chemical reaction Methods 0.000 claims description 37
- 239000003990 capacitor Substances 0.000 claims description 17
- 230000001360 synchronised effect Effects 0.000 description 12
- 230000003321 amplification Effects 0.000 description 7
- 238000003199 nucleic acid amplification method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000010355 oscillation Effects 0.000 description 4
- 239000000470 constituent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、入力信号が零の時に４１′４分出力が積分時
間に関係なく一定に保たれるようにした検波・積分回路
に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a detection/integration circuit in which the 41'4 output is kept constant regardless of the integration time when the input signal is zero.
従来の技術
従来の検波・積分回路では、第２図に示すようなブロッ
ク構成で同期検波・積分をすることがよく行われる。2. Description of the Related Art In conventional detection/integration circuits, synchronous detection/integration is often performed using a block configuration as shown in FIG.
ここでは、入力信号源１を信号増幅用電圧−電流変換ア
ンプ２の反転入力端子に入力し、同アンプ２の出力を同
期検波用電圧−電流変換アンプ４の反転入力端子および
オフセット検出用抵抗６を介してオペアンプ７の反転入
力端子に接続する。Here, the input signal source 1 is input to the inverting input terminal of the voltage-current conversion amplifier 2 for signal amplification, and the output of the amplifier 2 is input to the inverting input terminal of the voltage-current conversion amplifier 4 for synchronous detection and the offset detection resistor 6. It is connected to the inverting input terminal of the operational amplifier 7 via the inverting input terminal of the operational amplifier 7.
また、同期検波用電圧−電流変換アンプ４の出力を信号
増幅用電圧−電流変換アンプ２の非反転入力端子および
検波回路ホールド用コンデンサに接続する。他方、オペ
アンプ７０反転入力端子と出力端子との間に積分用コン
デンサ６を接続し、同オペアンプ７の出力を出力段バッ
ファ１ｏおよび積分用電圧−電流変換アンプ９の反転入
力端子にそれぞれ接続し、積分用電圧−電流変換アンプ
９の出力をオペアンプ７の非反転入力端子および積分回
路ホールド用コンデンサ８に接続する。そして、同期検
波用電圧−電流変換アンプ４および積分用電圧−電流変
換アンプ９の各非反転入力端子を基準電圧源に接続した
構成によシ検波・積分を行っている。Further, the output of the synchronous detection voltage-current conversion amplifier 4 is connected to the non-inverting input terminal of the signal amplification voltage-current conversion amplifier 2 and the detection circuit holding capacitor. On the other hand, an integrating capacitor 6 is connected between the inverting input terminal and the output terminal of the operational amplifier 70, and the output of the operational amplifier 7 is connected to the inverting input terminal of the output stage buffer 1o and the integrating voltage-current conversion amplifier 9, respectively. The output of the integrating voltage-current conversion amplifier 9 is connected to the non-inverting input terminal of the operational amplifier 7 and the integrating circuit holding capacitor 8. Detection and integration are performed by a configuration in which each of the non-inverting input terminals of the voltage-current conversion amplifier 4 for synchronous detection and the voltage-current conversion amplifier 9 for integration are connected to a reference voltage source.
発明が解決しようとする問題点
このような従来の回路では、オフセット検出用抵抗６の
値を大きくして検出能力を高めると、無用の発振を生じ
、一方、抵抗値を抑えて、発振を防止すると、オフセッ
ト検出性能が低下して正確に検波を行えず、積分出力が
階段状に現れないといった問題が生じ、正確な検波回路
を構成することが困難であった。Problems to be Solved by the Invention In such conventional circuits, if the value of the offset detection resistor 6 is increased to increase the detection capability, unnecessary oscillations occur, while on the other hand, it is necessary to suppress the resistance value to prevent oscillations. This causes a problem that the offset detection performance deteriorates, making it impossible to perform accurate detection, and that the integral output does not appear in a step-like manner, making it difficult to construct an accurate detection circuit.
本発明は、発振を抑え、高いオフセット検出性能をもつ
検波回路を構成することを目的としている。An object of the present invention is to suppress oscillation and configure a detection circuit having high offset detection performance.
問題点を解決するための手段
本発明では、まず、入力信号を第１の電圧−電流変換ア
ンプの反転・非反転入力の一方の端子に入力する。七の
出力電流を複数に分流して、そのうちの一の分流回路の
信号を第２の電圧−電流変換アンプの反転・非反転入力
の一方の端子に大願し、また抵抗を介してオペアンプの
反転・非反転入力の一方の端子に残余の分流出力電流信
号と共に入力接続する。第２の電圧−電流変換アンプの
出力は第１の電圧−電流変換アンプの他方の入力端子お
よび第１のコンデンサに接続する。オペアンプの一方の
入力端子と同オペアンプの出力端子との間に第２のコン
デンサを接続する。さらに、オペアンプの出力を出力段
バッファの入力端子および第３の電圧−電流変換アンプ
の反転・非反転入力の一方の端子にそれぞれ接続し、第
３の電圧−電流変換アンプの出力をオペアンプの他方の
入力端子および第３のコンデンサにそれぞれ接続する。Means for Solving the Problems In the present invention, first, an input signal is input to one terminal of the inverting/non-inverting input of the first voltage-current conversion amplifier. The output current of 7 is shunted into multiple circuits, and the signal from one of the shunt circuits is applied to one terminal of the inverting/non-inverting input of the second voltage-to-current converting amplifier, and is also connected to the inverting circuit of the operational amplifier via a resistor. -Connect the remaining shunt output current signal to one terminal of the non-inverting input. The output of the second voltage-current conversion amplifier is connected to the other input terminal of the first voltage-current conversion amplifier and the first capacitor. A second capacitor is connected between one input terminal of the operational amplifier and an output terminal of the same operational amplifier. Furthermore, the output of the operational amplifier is connected to the input terminal of the output stage buffer and one terminal of the inverting/non-inverting input of the third voltage-current conversion amplifier, and the output of the third voltage-current conversion amplifier is connected to the other terminal of the operational amplifier. and a third capacitor, respectively.
一方、第２の電圧−電流変換アンプおよび第３の電圧−
電流変換アンプの各他方の入力端子を基準電圧源に接続
して、検波会積分回路を構成している。On the other hand, the second voltage-current conversion amplifier and the third voltage-current conversion amplifier
Each other input terminal of the current conversion amplifier is connected to a reference voltage source to form a detection and integration circuit.
作 用
本発明によると発振が起こシにくく、検波が正確に行わ
れ、積分出力が正確に階段状に現われ、そのうえ、高利
得の検波・積分回路を実現することができる。According to the present invention, oscillation is difficult to occur, detection is performed accurately, the integral output appears accurately in a step-like manner, and moreover, a high-gain detection/integration circuit can be realized.
実施例
第１図ａは本発明の検波・積分回路の一実施例を示すブ
ロック図である。第１図ａにおいて、１は入力信号源、
２は複数の出力を有する信号増幅用電圧−電流変換アン
プ、３は検波回路ホールド用コンデンサ、４は同期検波
用電圧−電流変換アンプである。検波回路ホールド用コ
ンデンサ３は同期検波用電圧−電流変換アンプ４がオフ
している時、信号増幅用電圧−電流変換アンプ２と同期
検波用電圧−電流変換アンプ４のオフセラ）ｔ−補償す
るような電位を記憶している。また、５はオフセット検
出用抵抗であシ、信号増幅用電圧−電流変換アンプ２の
複数の出力のうちのひとつの出力電流による電圧降下に
より同期検波電圧−電流変換アンプ４の反転入力に電位
差を検知させる役割をしている。さらに、６は積分用コ
ンデンサ、７は積分回路を構成するオペアンプ、８は積
分回路ホールド用コンデンサ、９は積分用電圧−電流変
換アンプ、１０は出力段バッファであり、積分回路ホー
ルド用コンデンサ８は積分用電圧−電流変換アンプ９が
オフしている時、オペアンプ７のオフセットを補償する
ような電位を記憶している。Embodiment FIG. 1a is a block diagram showing an embodiment of the detection/integration circuit of the present invention. In FIG. 1a, 1 is an input signal source;
2 is a voltage-current conversion amplifier for signal amplification having a plurality of outputs, 3 is a capacitor for holding the detection circuit, and 4 is a voltage-current conversion amplifier for synchronous detection. The detection circuit hold capacitor 3 is designed to compensate for the voltage-current conversion amplifier 2 for signal amplification and the voltage-current conversion amplifier 4 for synchronous detection when the voltage-current conversion amplifier 4 for synchronous detection is off. The electric potential is memorized. Further, 5 is an offset detection resistor, which applies a potential difference to the inverting input of the synchronous detection voltage-current conversion amplifier 4 due to a voltage drop caused by the output current of one of the plurality of outputs of the signal amplification voltage-current conversion amplifier 2. It plays the role of detection. Further, 6 is an integrating capacitor, 7 is an operational amplifier forming the integrating circuit, 8 is an integrating circuit holding capacitor, 9 is an integrating voltage-current conversion amplifier, 10 is an output stage buffer, and the integrating circuit holding capacitor 8 is When the integrating voltage-current conversion amplifier 9 is off, a potential that compensates for the offset of the operational amplifier 7 is stored.
なお、出力段のバッファ１ｏは通常のオペアンプの出力
−反転入力端子間を接続して、非反転入力端子に信号を
与える構成である。Note that the output stage buffer 1o has a configuration in which the output of an ordinary operational amplifier is connected to an inverting input terminal and a signal is provided to a non-inverting input terminal.
そして、第１図中に付記した動作タイミング波形を説明
すると、１１は入力信号、１２は同期検波用電圧−電流
変換アンプ４へのスイッチング信号であシ、入力信号１
１と同期しているもの、１３は積分用電圧−電流変換ア
ンプ９へのスイッチング信号であシ、入力信号が入力さ
れると同時にオフし積分時間を決めるもの、１４は出力
電圧である。なお、出力電圧１４の波形は本来階段状に
なるものであるが、作図上の煩雑さから、それを省略し
ている。To explain the operation timing waveforms added in FIG. 1, 11 is an input signal, 12 is a switching signal to the voltage-current conversion amplifier 4 for synchronous detection, and input signal 1
1 is synchronized with 1, 13 is a switching signal to the voltage-to-current conversion amplifier 9 for integration, and is turned off at the same time as the input signal is input to determine the integration time; 14 is the output voltage. Note that although the waveform of the output voltage 14 originally has a step-like shape, it is omitted for the sake of complexity in drawing.
また、第１図すは本発明の検波・積分回路の他の一実施
例であるが、第１図ａの構成の信号増幅用電圧−電流変
換アンプの反転入力と非反転入力および同期検波用電圧
−電流変換アンプの反転入力と非反転入力をそれぞれ逆
にしたものである。FIG. 1 shows another embodiment of the detection/integration circuit of the present invention, and the inverting input and non-inverting input of the voltage-to-current conversion amplifier for signal amplification having the configuration shown in FIG. 1a and the synchronous detection The inverting input and non-inverting input of the voltage-to-current conversion amplifier are reversed.
発明の効果
以上のように、本発明によれば、構成するアンプのオフ
セットに関係なく精度の良い検波・積分が行われる。ま
た、高利得でも発振せず、正確な検波が実現できて実用
的にきわめて有用である。Effects of the Invention As described above, according to the present invention, accurate detection and integration can be performed regardless of the offset of the constituent amplifiers. In addition, it does not oscillate even at high gain, and accurate detection can be achieved, making it extremely useful in practice.
第１図ａ、ｂは本発明の一実施例における検波・積分回
路を示すブロック図および動作タイミング図、第２図は
従来例の検波・積分回路を示すブロック図および動作タ
イミング図であ。
１・・・・・・入力信号源、２・・・・・・信号増幅用
電圧、３・・・・・・検波回路ホールド用コンデンサ、
４・・・・・・同期検波用電圧−電流変換アンプ、５・
・・・・・オフセット検出用抵抗、６・・・・・・積分
用コンデンサ、７・・・・・・オペアンプ、８・・・・
・・積分回路ホールド用コンデンサ、９・・・・・・積
分用電圧−電流変換アンプ、１ｏ・・・・・・出力段の
バッファ。1A and 1B are a block diagram and an operation timing diagram showing a detection/integration circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram and an operation timing diagram showing a conventional detection/integration circuit. 1...Input signal source, 2...Voltage for signal amplification, 3...Capacitor for holding the detection circuit,
4...Voltage-current conversion amplifier for synchronous detection, 5.
...Offset detection resistor, 6... Integrating capacitor, 7... Operational amplifier, 8...
... Integrating circuit hold capacitor, 9... Integrating voltage-current conversion amplifier, 1o... Output stage buffer.
Claims (1)
入力の一方の端子に入力し、その出力電流を複数に分流
して、そのうちの一の分流回路の信号を第２の電圧−電
流変換アンプの反転・非反転入力の一方の端子、および
抵抗を介してオペアンプの反転・非反転入力の一方の端
子に残余の前記分流出力電流信号と共に入力接続し、前
記第２の電圧−電流変換アンプの出力を前記第１の電圧
−電流変換アンプの他方の入力端子および第１のコンデ
ンサに接続し、前記オペアンプの一方の入力端子と同オ
ペアンプの出力端子との間に第２のコンデンサを接続し
、前記オペアンプの出力を出力段バッファの入力端子お
よび第３の電圧−電流変換アンプの反転・非反転入力の
一方の端子にそれぞれ接続し、前記第３の電圧−電流変
換アンプの出力を前記オペアンプの他方の入力端子およ
び第３のコンデンサにそれぞれ接続し、前記第２の電圧
−電流変換アンプおよび前記第３の電圧−電流変換アン
プの各他方の入力端子を基準電圧源に接続して構成した
検波・積分回路。An input signal is input to one terminal of the inverting/non-inverting input of the first voltage-current conversion amplifier, the output current is divided into multiple circuits, and the signal from one of the shunt circuits is converted to the second voltage-current converter. The remaining shunt output current signal is connected to one terminal of the inverting/non-inverting input of the conversion amplifier and one terminal of the inverting/non-inverting input of the operational amplifier via a resistor, and the second voltage-to-current conversion is performed. An output of the amplifier is connected to the other input terminal of the first voltage-current conversion amplifier and a first capacitor, and a second capacitor is connected between the one input terminal of the operational amplifier and the output terminal of the operational amplifier. The output of the operational amplifier is connected to the input terminal of the output stage buffer and one terminal of the inverting/non-inverting input of the third voltage-current converting amplifier, and the output of the third voltage-current converting amplifier is connected to the The other input terminal of the operational amplifier and the third capacitor are connected to each other, and the other input terminals of the second voltage-current conversion amplifier and the third voltage-current conversion amplifier are connected to a reference voltage source. Detection/integration circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3233586A JPS62189804A (en) | 1986-02-17 | 1986-02-17 | Detection and integration circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3233586A JPS62189804A (en) | 1986-02-17 | 1986-02-17 | Detection and integration circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62189804A true JPS62189804A (en) | 1987-08-19 |
Family
ID=12356081
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3233586A Pending JPS62189804A (en) | 1986-02-17 | 1986-02-17 | Detection and integration circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62189804A (en) |
-
1986
- 1986-02-17 JP JP3233586A patent/JPS62189804A/en active Pending
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