JPS62188589A - Lottery grid shape switch - Google Patents

Lottery grid shape switch

Info

Publication number
JPS62188589A
JPS62188589A JP3054686A JP3054686A JPS62188589A JP S62188589 A JPS62188589 A JP S62188589A JP 3054686 A JP3054686 A JP 3054686A JP 3054686 A JP3054686 A JP 3054686A JP S62188589 A JPS62188589 A JP S62188589A
Authority
JP
Japan
Prior art keywords
switch
passes
input terminal
input
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3054686A
Other languages
Japanese (ja)
Other versions
JPH0714225B2 (en
Inventor
Kenichi Yukimatsu
健一 行松
Hiroshi Fujitani
宏 藤谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP61030546A priority Critical patent/JPH0714225B2/en
Publication of JPS62188589A publication Critical patent/JPS62188589A/en
Publication of JPH0714225B2 publication Critical patent/JPH0714225B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To attain a switch having no internal congestion with the number of switch elements fewer than a complete grid type switch by providing the number of the switch elements brought into a cross connection during an ON state and into a through connection during an OFF state which can be connected without the internal congestion by input and output terminals. CONSTITUTION:The fewest number (m) of passes required for making a lottery grid shape switch having (n) input terminals and (n) output terminals to make the switch having no internal congestion is the number of the combination selecting two from (n), namely nC2 and the passes of m(=nC2) are disposed. Namely, the passes are disposed so as to make all the combinations of input terminal numbers applied to the respective passes different in case of applying the input terminal numbers 1-4 using from the upper part to the lower part of the respective passes and the input terminal numbers using from the lower part to the upper part to the respective passes with all the (n) passes brought into the ON state. Thereby, the lottery grid shape switch becomes the switch having no internal congestion.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、複数の入端子と複数の出端子とをそれぞれ内
部輻棲なく接続する交換スイッチに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an exchange switch that connects a plurality of input terminals and a plurality of output terminals without internal congestion.

〔従来の技術〕[Conventional technology]

従来は、n個の入端子とn個の出端子を内部輻棲なく接
続できる交換スイッチとして、nXnの完全格子形スイ
ッチが知られている。この完全格子形スイッチでは端子
数の増加に伴って格子点数がn!で増加する。そこで、
これを解決するスイッチ構成として、多段のスイッチ構
成にすることによシ格子点数を減らす方法が提案されて
いる(文献+  Charles (31os :’ 
A 5tudy of Non −Blocking8
wltching Network’+  the B
e1l System TechnicalJourn
al + march / 9 ! j + pp、≠
OA −41211)1.この種のスイッチ(以下、0
1os形スイツチと呼ぶ)は入端子と出端子を新たに接
続するときに、空きのパスがなければ、既に接続してい
る1(スを再配置するようにして、完全格子形スイッチ
よシ少ない格子点で内部輻棲のないスイッチ構成をとっ
ているものである。
Conventionally, an nXn complete lattice type switch has been known as an exchange switch that can connect n input terminals and n output terminals without internal congestion. In this complete lattice switch, the number of lattice points increases to n! as the number of terminals increases. increases with Therefore,
As a switch configuration to solve this problem, a method has been proposed to reduce the number of grid points by using a multi-stage switch configuration (Reference + Charles (31os:'
A 5tudy of Non-Blocking8
Wltching Network'+ the B
e1l System Technical Journal
al + march / 9! j + pp, ≠
OA-41211)1. This type of switch (hereinafter referred to as 0
When newly connecting an input terminal and an output terminal, a 1OS type switch (called a 1OS type switch) can be used to connect an input terminal and an output terminal, and if there is no free path, it is possible to rearrange the already connected 1 (OS type switch). It has a switch configuration with no internal radiation at grid points.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の完全格子形スイッチは端子数の増加に伴って格子
点数が急速に増加しスイッチコストが高くなるので、ス
イッチサイズの小さい所でしか用いることができない。
Conventional full lattice type switches can only be used in places where the switch size is small because the number of lattice points increases rapidly as the number of terminals increases and the switch cost increases.

一方、Olos形スイッチにおいても、完全格子形スイ
ッチより少ない格子点で内部輻積のないスイッチが構成
できるのは端子数が2≠以上の場合であ夛、それより端
子数が少ない場合には効果がないという欠点がある。
On the other hand, even with Olos type switches, it is possible to configure a switch without internal congestion with fewer lattice points than with a complete lattice type switch when the number of terminals is 2≠ or more, and it is effective when the number of terminals is smaller than that. The disadvantage is that there is no

本発明の目的は、従来方式よシ少ない数のスイッチ素子
(格子点に置くスイッチ素子のこと)でスイッチサイズ
が小さい所から大きい所まで適用できる内部輻羨のない
nXnの交換スイッチを提供することにある。
An object of the present invention is to provide an nXn exchange switch that can be applied to a range of switch sizes from small to large, with a smaller number of switch elements (switch elements placed at lattice points) than the conventional system, and is free from internal convergence. It is in.

〔問題点を解決するための手段及び作用〕本発明は、上
記問題点を解決するために、n個の入端子とn個の出端
子との間をl対lに接続して片方向に信号を伝達するn
個のリンクと、ON状態のときクロス接続となfi O
FF状態のときスルー接続となる2×−のスイッチ素子
とがらなり、該スイッチ素子を入出力端子相互で内部輻
椿なく接続できる個数だけ設けている。
[Means and effects for solving the problems] In order to solve the above problems, the present invention provides a unidirectional connection between n input terminals and n output terminals by connecting them in a l-to-l manner. n to transmit a signal
When the links are in the ON state, they are cross-connected.
There are 2×- switch elements which are through-connected when in the FF state, and the number of switch elements that can be connected between the input and output terminals without internal congestion is provided.

これによって、前記の完全格子形スイッチのスイッチ素
子数n2よシ少ない nCt個のスイッチ素子で内部輻
棲のないスイッチが構成できるとともに、前記のOIo
s形スイッチと異なシ、端子数nが24A未満の場合で
も完全格子形スイッチより少ないスイッチ素子数で内部
輻棲のないスイッチが構成できる。
As a result, it is possible to configure a switch without internal interference with nCt switching elements, which is smaller than the number n2 of switching elements of the above-mentioned complete lattice switch, and also to
Unlike an S-type switch, even when the number of terminals n is less than 24A, a switch without internal interference can be constructed with fewer switching elements than a complete lattice switch.

〔実施例〕〔Example〕

第1図は、あみだ形スイッチの概念を説明する図であッ
テ、tol、tol、103.104cは入端子、//
/l  itx*  //J、tt≠は出端子、/J/
、/2コ、123./コ≠はリンク、/J/、/Jλ+
IJJ−13≠、t3j、tstsはスイッチ素子(以
後、パスと呼ぶ)である、第1図において、例えば入端
子102と出端子/l弘を接続する場合は、パス/33
及びパス13jをONにし、パス/36はOFFにする
。その他のパスは0N10FFいずれでも良いが、パス
/36がONであると入端子10コは出端子//Jに接
続されることになる。入端子loコと、出端子iiu@
接続する方法は一通シではなく、パス134にとパス/
 J A ’i ON 、パ、’、133とパス/ J
 / t−0FF(その他のパスは、0N10FFいず
れでも良い)としても良い、前述の通り、パス/JJ及
びパス13J″をONにし、その他のパスはすべてOF
F とすると、他の入端子ioi*  to3s  i
o≠はそれぞれ出端子///、//Jl  //Jに接
続されることとなる。実際には、パスは例えばi2図に
示すようなスイッチ素子を使うことによって実現できる
。fjgコ図のスイッチ素子は、0N10FFの2状態
を持ち、OFFの場合は入端子コIIと出端子221、
入端子−lコと出端子コココとを接続し、ONの場合は
入端子コ//と出端子コ2λ、入端子21.2と出端子
221とを接続するものである。
Figure 1 is a diagram explaining the concept of an amida-type switch. Atte, tol, tol, 103.104c are input terminals, //
/l itx* //J, tt≠ is the output terminal, /J/
, /2 pieces, 123. /ko≠ is a link, /J/, /Jλ+
IJJ-13≠, t3j, tsts are switch elements (hereinafter referred to as paths). In FIG. 1, for example, when connecting the input terminal 102 and the output terminal /lhiro,
Then, the path 13j is turned ON, and the path /36 is turned OFF. The other paths may be 0N10FF, but if path /36 is ON, the 10 input terminals will be connected to the output terminal /J. Input terminal loko and output terminal iiu@
The connection method is not one way, but path 134 and path/
J A 'i ON, pa, ', 133 and pass/J
/ t-0FF (Other paths can be 0N10FF) As mentioned above, turn on path /JJ and path 13J'', and turn all other paths off.
F, other input terminal ioi* to3s i
o≠ will be connected to the output terminals /// and //Jl //J, respectively. In practice, the path can be realized, for example, by using a switching element as shown in Figure i2. The switch element in the fjg diagram has two states: 0N10FF, and when it is OFF, the input terminal II and the output terminal 221,
It connects the input terminal -l and the output terminal here, and when it is ON, connects the input terminal // and the output terminal 2λ, and the input terminal 21.2 and the output terminal 221.

第2図のスイッチ素子を用いた場合の第1図のスイッチ
の構成例を、第3図に示す、第3図は、すべてのパスが
ONの状態を示している。
FIG. 3 shows an example of the configuration of the switch shown in FIG. 1 using the switch element shown in FIG. 2. FIG. 3 shows a state in which all paths are ON.

次に、内部輻積のないあみだ形スイッチの構成方法につ
いて説明する。ここで、内部輻積のないスイッチとは、
任意の入端子及び出端子がそれぞれ空であれば、他の入
端子と出端子間がどのように接続されていても、該入端
子と該出端子とを接続することが可能なスイッチのこと
である。但し、新たな接続路を設定するにあfcうて、
既に接続路が設定されている入端子と出端子について、
接続関係は変更しないがパスは新たに設定しなおす(パ
スの再配置)必要がある場合も、ここでは内部輻饋なし
とする。第μ図は、入端子、出端子の数がそれぞれダの
場合について、内部輻棲のないあみだ形スイッチの構成
例を示すものである。第φ図において、140/、11
02.1A03.IAOIAは入端子、μ//、≠t2
+ ttiJ+ ≠lμは出端子、≠、21.≠22.
≠23.≠2弘はリンク、lA3 /、 ≠32.≠3
3.lA3弘、≠3よ、≠36はパスであシ、リンク、
パスは8g1図を用いて既に説明し六通りの機能を持つ
ものである。一般に、n個の入端子とn個の出端子を持
つあみだ形スイッチを内部輻棒のないスイッチにするの
に必要な最小限のパスの数(m)は、n個から2個を選
ぶ組み合わせの数、即ちnC2であり、m(=nC2)
個のパスを以下に述べる規則に従って配置すれば、内部
輻棲のないあみだ族スイッチが構成できる。
Next, a method of constructing a mid-shaped switch with no internal radiation will be explained. Here, a switch without internal congestion is
A switch that can connect any input terminal and output terminal, if each input terminal and output terminal are empty, regardless of how other input terminals and output terminals are connected. It is. However, when setting up a new connection route,
For input and output terminals for which connection paths have already been set,
Even if the connection relationship is not changed but the path needs to be newly set (path relocation), no internal interference is assumed here. FIG. μ shows an example of the structure of a cross-shaped switch with no internal interference when the number of input terminals and the number of output terminals are respectively Da. In Fig. φ, 140/, 11
02.1A03. IAOIA is the input terminal, μ//, ≠t2
+ttiJ+ ≠lμ is the output terminal, ≠, 21. ≠22.
≠23. ≠2 Hiro is a link, lA3 /, ≠32. ≠3
3. lA3hiro, ≠3, ≠36 is a path, link,
The path has six functions, which have already been explained using the 8g1 diagram. In general, the minimum number of paths (m) required to make a cross-shaped switch with n input terminals and n output terminals into a switch without internal rods is selected from n to 2. The number of combinations, that is, nC2, m (= nC2)
By arranging the paths according to the rules described below, an Amida family switch without internal congestion can be constructed.

即ち、m個のパスについて、すべてのパスをONにした
状態で、各パスを図の上から下へ使用する入端子番号(
第≠図で、■〜■)及び下から上へ使用する入端子番号
をそれぞれのパスに付与した時、各パスに付与された入
端子番号の組み合わせがすべて異なるようにパスを配貨
すると、該あみだ形スイッチは内部輻積のないスイッチ
となる。
In other words, for m paths, with all paths turned on, input terminal numbers (
In Figure ≠, when assigning input terminal numbers (■ to ■) and input terminal numbers used from bottom to top to each pass, if the passes are distributed so that the combinations of input terminal numbers assigned to each pass are all different, The cross-shaped switch is a switch with no internal interference.

第μ図は、この条件を満足しており、内部輻積はない。Figure μ satisfies this condition and there is no internal radiation.

第1図もこの条件を満足する構成になっておシ、内部輻
榛はない。
The structure shown in FIG. 1 also satisfies this condition, and there is no internal radiation.

以上の説明ではリンクは片方向として説明したが、時分
割多重等通常知られている方法によって上りと下シの信
号を多重化して伝送する方法をとれば、本発明のあみだ
形スイッチを用いて各入端子と出端子との間で双方向の
信号を伝送するのは容易である。また、同一構成のあみ
だ形スイッチを2面用意し、それぞれ対応するパスを同
時に0N10FFすることによって、双方向のあみだ形
スイッチを構成することも容易である。
In the above explanation, the link was explained as being unidirectional, but if a method of multiplexing and transmitting uplink and downlink signals by a commonly known method such as time division multiplexing is used, the mid-shaped switch of the present invention can be used. It is easy to transmit bidirectional signals between each input terminal and output terminal. Furthermore, it is easy to construct a bidirectional cross-section switch by preparing two sides of the cross-section switch having the same configuration and turning the corresponding paths to 0N10FF at the same time.

〔発明の効果〕〔Effect of the invention〕

以上説明し六ように、本発明によれば、完全格子形スイ
ッチに比べて少ない数のスイッチ素子で、内部輻棲のな
いスイッチが構成できるという利点がある。本発明の場
合のスイッチ素子は、完全格子形スイッチのようなゲー
トスイッチではないが、第2図に示したようなスイッチ
素子としては、方向性結合形ないし反射形の元スイッチ
等があシ、これらのスイッチ素子を用いて容易に構成す
ることができる。
As explained above, the present invention has the advantage that it is possible to configure a switch without internal radiation with a smaller number of switch elements than a complete lattice switch. The switch element in the case of the present invention is not a gate switch like a complete lattice switch, but the switch element shown in FIG. 2 may be a directional coupling type or reflection type original switch, etc. It can be easily configured using these switching elements.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はあみだ形スイッチの概念説明図、第2図はパス
を実現するスイッチ素子の構成例、M3図はあみだ形ス
イッチの一実施例、第≠図は内部輻斡のないあみだ形ス
イッチの一構成例である。
Figure 1 is a diagram explaining the concept of a middle-shaped switch, Figure 2 is an example of the configuration of a switch element that realizes a path, M3 is an example of a middle-shaped switch, and Figure ≠ is a middle-shaped switch with no internal interference. This is an example of a configuration of a type switch.

Claims (2)

【特許請求の範囲】[Claims] (1)n個の入端子とn個の出端子との間を1対1に接
続して片方向に信号を伝達するリンクと、2本のリンク
間にあってOFF状態では2本のリンクをスルーに接続
しON状態では2本のリンクをクロスに接続するスイッ
チ素子とからなり、該スイッチ素子を入出力端子相互で
内部輻輳なく接続できる個数だけ設けたことを特徴とす
るあみだ形スイッチ。
(1) A link that connects n input terminals and n output terminals one-to-one and transmits signals in one direction, and a link that is between two links and passes through the two links when in the OFF state. 1. A mid-shaped switch comprising a switching element which connects two links crosswise in an ON state, and is characterized in that the number of such switching elements is such that the input and output terminals can be connected to each other without internal congestion.
(2)前記スイッチ素子をnC_2個設けたことを特徴
とする特許請求の範囲第1項記載のあみだ形スイッチ。
(2) The cross-shaped switch according to claim 1, characterized in that nC_2 switching elements are provided.
JP61030546A 1986-02-14 1986-02-14 Replacement switch Expired - Lifetime JPH0714225B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61030546A JPH0714225B2 (en) 1986-02-14 1986-02-14 Replacement switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61030546A JPH0714225B2 (en) 1986-02-14 1986-02-14 Replacement switch

Publications (2)

Publication Number Publication Date
JPS62188589A true JPS62188589A (en) 1987-08-18
JPH0714225B2 JPH0714225B2 (en) 1995-02-15

Family

ID=12306789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61030546A Expired - Lifetime JPH0714225B2 (en) 1986-02-14 1986-02-14 Replacement switch

Country Status (1)

Country Link
JP (1) JPH0714225B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1152632A2 (en) * 2000-05-05 2001-11-07 Cronos Integrated Microsystems, Inc. Microelectromechanical optical cross-connect switches having reduced numbers of reflectors

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5945423A (en) * 1982-09-07 1984-03-14 Nec Corp Matrix optical switch and its driving method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5945423A (en) * 1982-09-07 1984-03-14 Nec Corp Matrix optical switch and its driving method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1152632A2 (en) * 2000-05-05 2001-11-07 Cronos Integrated Microsystems, Inc. Microelectromechanical optical cross-connect switches having reduced numbers of reflectors
EP1152632A3 (en) * 2000-05-05 2003-10-15 Memscap S.A. Microelectromechanical optical cross-connect switches having reduced numbers of reflectors

Also Published As

Publication number Publication date
JPH0714225B2 (en) 1995-02-15

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