WO1988006764A3 - Massively parallel array processing system - Google Patents

Massively parallel array processing system Download PDF

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Publication number
WO1988006764A3
WO1988006764A3 PCT/US1988/000456 US8800456W WO8806764A3 WO 1988006764 A3 WO1988006764 A3 WO 1988006764A3 US 8800456 W US8800456 W US 8800456W WO 8806764 A3 WO8806764 A3 WO 8806764A3
Authority
WO
WIPO (PCT)
Prior art keywords
processing elements
path
processing
stage
processor
Prior art date
Application number
PCT/US1988/000456
Other languages
French (fr)
Other versions
WO1988006764A2 (en
Inventor
Robert S Grondalski
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Priority to JP50420988A priority Critical patent/JPH02503243A/en
Publication of WO1988006764A2 publication Critical patent/WO1988006764A2/en
Publication of WO1988006764A3 publication Critical patent/WO1988006764A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17381—Two dimensional, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus

Abstract

An array processing system including a plurality of processing elements each including a processor (22A) and an associated memory module (23A), the system further including a router network (30) over which each processing element can transfer messages to other random processing elements, a mechanism by which a processor can transmit data to one of four nearest-neighbor processors. In addition, the processing elements are divided into groups each with four processing elements, in which one of the processing elements can access data in the other processing elements' memory modules. The routing network switches messages in a plurality of switching stages, with each stage connecting to the next stage through communications paths that are divided into groups, each group, in turn being associated with selected address signals. A communications path continuity test circuit associated with each path detects any discontinuity in the communications path and disables the path. Thus, the stage may attempt to transfer a message over another path associated with the same address.
PCT/US1988/000456 1987-02-24 1988-02-16 Massively parallel array processing system WO1988006764A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50420988A JPH02503243A (en) 1988-02-16 1988-02-16 Large-scale parallel array processing device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US018,937 1987-02-24
US1893787A 1987-02-25 1987-02-25

Publications (2)

Publication Number Publication Date
WO1988006764A2 WO1988006764A2 (en) 1988-09-07
WO1988006764A3 true WO1988006764A3 (en) 1988-12-15

Family

ID=21790510

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1988/000456 WO1988006764A2 (en) 1987-02-24 1988-02-16 Massively parallel array processing system

Country Status (3)

Country Link
EP (1) EP0303696A1 (en)
CA (1) CA1312960C (en)
WO (1) WO1988006764A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280474A (en) * 1990-01-05 1994-01-18 Maspar Computer Corporation Scalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arrays
US5313590A (en) * 1990-01-05 1994-05-17 Maspar Computer Corporation System having fixedly priorized and grouped by positions I/O lines for interconnecting router elements in plurality of stages within parrallel computer
AU645785B2 (en) * 1990-01-05 1994-01-27 Maspar Computer Corporation Parallel processor memory system
EP0509058A4 (en) * 1990-01-05 1993-11-18 Maspar Computer Corporation Router chip with quad-crossbar and hyperbar personalities
US5243699A (en) * 1991-12-06 1993-09-07 Maspar Computer Corporation Input/output system for parallel processing arrays
US6266342B1 (en) * 1998-04-08 2001-07-24 Nortel Networks Limited Adaption resource module and operating method therefor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4051551A (en) * 1976-05-03 1977-09-27 Burroughs Corporation Multidimensional parallel access computer memory system
WO1983002180A1 (en) * 1981-12-14 1983-06-23 Western Electric Co Interface processor unit
EP0171856A1 (en) * 1984-08-14 1986-02-19 Telecommunications Radioelectriques Et Telephoniques T.R.T. Signal processor and hierarchical multiprocessing structure comprising at least one such processor
EP0261034A2 (en) * 1986-09-18 1988-03-23 Digital Equipment Corporation Massively parallel array processing system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4051551A (en) * 1976-05-03 1977-09-27 Burroughs Corporation Multidimensional parallel access computer memory system
WO1983002180A1 (en) * 1981-12-14 1983-06-23 Western Electric Co Interface processor unit
EP0171856A1 (en) * 1984-08-14 1986-02-19 Telecommunications Radioelectriques Et Telephoniques T.R.T. Signal processor and hierarchical multiprocessing structure comprising at least one such processor
EP0261034A2 (en) * 1986-09-18 1988-03-23 Digital Equipment Corporation Massively parallel array processing system

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Patent Abstracts of Japan, volume 7, no. 121 (P-199)(1266), 25 May 1983; & JP-A-5839360 (TOKYO SHIBAURA DENKI K.K.) 8 March 1983 *
Wescon Technical Papers, 30 October - 2 November 1984, (Anaheim, California, US), B. Beims: "Multiprocessing capabilities of the MC68020 32-bit Microprocessor", pages 1-16 *

Also Published As

Publication number Publication date
CA1312960C (en) 1993-01-19
EP0303696A1 (en) 1989-02-22
WO1988006764A2 (en) 1988-09-07

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