WO1988006764A3 - Systeme de processeurs vectoriels paralleles en grand nombre - Google Patents
Systeme de processeurs vectoriels paralleles en grand nombre Download PDFInfo
- Publication number
- WO1988006764A3 WO1988006764A3 PCT/US1988/000456 US8800456W WO8806764A3 WO 1988006764 A3 WO1988006764 A3 WO 1988006764A3 US 8800456 W US8800456 W US 8800456W WO 8806764 A3 WO8806764 A3 WO 8806764A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- processing elements
- path
- processing
- stage
- processor
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
- G06F15/17381—Two dimensional, e.g. mesh, torus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
- G06F15/8023—Two dimensional arrays, e.g. mesh, torus
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Multi Processors (AREA)
Abstract
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50420988A JPH02503243A (ja) | 1988-02-16 | 1988-02-16 | 大規模並列アレイ処理装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US018,937 | 1987-02-24 | ||
US1893787A | 1987-02-25 | 1987-02-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1988006764A2 WO1988006764A2 (fr) | 1988-09-07 |
WO1988006764A3 true WO1988006764A3 (fr) | 1988-12-15 |
Family
ID=21790510
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1988/000456 WO1988006764A2 (fr) | 1987-02-24 | 1988-02-16 | Systeme de processeurs vectoriels paralleles en grand nombre |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0303696A1 (fr) |
CA (1) | CA1312960C (fr) |
WO (1) | WO1988006764A2 (fr) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0509055A4 (en) * | 1990-01-05 | 1994-07-27 | Maspar Computer Corp | Parallel processor memory system |
EP0509058A4 (en) * | 1990-01-05 | 1993-11-18 | Maspar Computer Corporation | Router chip with quad-crossbar and hyperbar personalities |
US5280474A (en) * | 1990-01-05 | 1994-01-18 | Maspar Computer Corporation | Scalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arrays |
US5313590A (en) * | 1990-01-05 | 1994-05-17 | Maspar Computer Corporation | System having fixedly priorized and grouped by positions I/O lines for interconnecting router elements in plurality of stages within parrallel computer |
US5243699A (en) * | 1991-12-06 | 1993-09-07 | Maspar Computer Corporation | Input/output system for parallel processing arrays |
US6266342B1 (en) * | 1998-04-08 | 2001-07-24 | Nortel Networks Limited | Adaption resource module and operating method therefor |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4051551A (en) * | 1976-05-03 | 1977-09-27 | Burroughs Corporation | Multidimensional parallel access computer memory system |
WO1983002180A1 (fr) * | 1981-12-14 | 1983-06-23 | Western Electric Co | Unite de processeur d'interface |
EP0171856A1 (fr) * | 1984-08-14 | 1986-02-19 | Telecommunications Radioelectriques Et Telephoniques T.R.T. | Processeur pour le traitement de signal et structure de multitraitement hiérarchisée comportant au moins un tel processeur |
EP0261034A2 (fr) * | 1986-09-18 | 1988-03-23 | Digital Equipment Corporation | Système massif de réseau de processeurs parallèles |
-
1988
- 1988-02-16 WO PCT/US1988/000456 patent/WO1988006764A2/fr not_active Application Discontinuation
- 1988-02-16 EP EP19880904720 patent/EP0303696A1/fr not_active Withdrawn
- 1988-02-23 CA CA000559528A patent/CA1312960C/fr not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4051551A (en) * | 1976-05-03 | 1977-09-27 | Burroughs Corporation | Multidimensional parallel access computer memory system |
WO1983002180A1 (fr) * | 1981-12-14 | 1983-06-23 | Western Electric Co | Unite de processeur d'interface |
EP0171856A1 (fr) * | 1984-08-14 | 1986-02-19 | Telecommunications Radioelectriques Et Telephoniques T.R.T. | Processeur pour le traitement de signal et structure de multitraitement hiérarchisée comportant au moins un tel processeur |
EP0261034A2 (fr) * | 1986-09-18 | 1988-03-23 | Digital Equipment Corporation | Système massif de réseau de processeurs parallèles |
Non-Patent Citations (2)
Title |
---|
Patent Abstracts of Japan, volume 7, no. 121 (P-199)(1266), 25 May 1983; & JP-A-5839360 (TOKYO SHIBAURA DENKI K.K.) 8 March 1983 * |
Wescon Technical Papers, 30 October - 2 November 1984, (Anaheim, California, US), B. Beims: "Multiprocessing capabilities of the MC68020 32-bit Microprocessor", pages 1-16 * |
Also Published As
Publication number | Publication date |
---|---|
CA1312960C (fr) | 1993-01-19 |
EP0303696A1 (fr) | 1989-02-22 |
WO1988006764A2 (fr) | 1988-09-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0261034A3 (fr) | Système massif de réseau de processeurs parallèles | |
US4063083A (en) | Data communication system using light coupled interfaces | |
EP0371772B1 (fr) | Réseau de commutation pour accès à une mémoire | |
SU1321383A3 (ru) | Цифровое коммутационное устройство | |
US4270170A (en) | Array processor | |
US4984237A (en) | Multistage network with distributed pipelined control | |
US7715369B1 (en) | Common backplane for physical layer system and networking layer system | |
WO1999011104B1 (fr) | Procede d'interconnexion electronique et appareil permettant de raccourcir les temps de propagation | |
JPS6340383B2 (fr) | ||
US4270169A (en) | Array processor | |
EP0240211A3 (fr) | Réseau de commutation | |
ATE40501T1 (de) | Mehrfachspeicher-ladesystem. | |
US20240045821A1 (en) | Multi-path server and multi-path server signal interconnection system | |
WO1988006764A3 (fr) | Systeme de processeurs vectoriels paralleles en grand nombre | |
US5065394A (en) | Packet routing switch | |
US20040093404A1 (en) | Protocol for identifying components in a point-to-point computer system | |
CA2041202C (fr) | Reseau de communication numerique a extensibilite en canaux illimitees | |
AU687559B2 (en) | Time switch system | |
Minsky et al. | RN1: Low-latency, dilated, crossbar router | |
CA1154132A (fr) | Appareil d'interconnexion pour systeme telephonique a commutation repartie | |
SE8900674D0 (sv) | Stjaernformigt datanaet med logisk ringfunktion utnyttjande foeretraedesvis token-access | |
KR0181117B1 (ko) | 비-버스 입출력부에서 직접 메모리 접근부를 사용한 직렬통신 장치 | |
KR970049736A (ko) | 병렬처리 컴퓨터 시스템에서 크로스바 스위치를 사용한 클러스터 연결구조 | |
Ruighaver | Reconfigurable optical interconnection networks without optical switching | |
KR200325540Y1 (ko) | 24×24 넌블록킹 스위칭 매트릭스 회로 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): JP |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH DE FR GB IT LU NL SE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1988904720 Country of ref document: EP |
|
AK | Designated states |
Kind code of ref document: A3 Designated state(s): JP |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): AT BE CH DE FR GB IT LU NL SE |
|
WWP | Wipo information: published in national office |
Ref document number: 1988904720 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1988904720 Country of ref document: EP |