JPS62188582A - Gain control circuit for video frequency amplifier - Google Patents
Gain control circuit for video frequency amplifierInfo
- Publication number
- JPS62188582A JPS62188582A JP61031062A JP3106286A JPS62188582A JP S62188582 A JPS62188582 A JP S62188582A JP 61031062 A JP61031062 A JP 61031062A JP 3106286 A JP3106286 A JP 3106286A JP S62188582 A JPS62188582 A JP S62188582A
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- Japan
- Prior art keywords
- signal
- video
- superimposed
- gain control
- gain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000605 extraction Methods 0.000 claims description 8
- 238000001514 detection method Methods 0.000 claims description 2
- 238000005070 sampling Methods 0.000 abstract 2
- 230000003321 amplification Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
Landscapes
- Processing Of Color Television Signals (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、複数個の映像増幅器の利得を同時に変化さ
せる時、その変化量が常に等しくなるように制御する回
路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit that controls the gains of a plurality of video amplifiers so that when the gains are changed simultaneously, the amount of change is always equal.
第2図は従来の映像増幅回路に関するものである。この
従来例では映像増幅器がR−G−Bの3つの信号に対し
3つ設けられている場合について述べる0図において、
lr、Ig、lbは各々R1G、B信号入力端子、2r
、2g、2bは各々R1G、B映像増幅器、3r、3g
、3bは各々R1G、B信号出力端子、R1,R2,R
3,R4は抵抗器、VRl、VH2,VH2は可変抵抗
器である。また4r、4g、4bはそれぞれR,G。FIG. 2 relates to a conventional video amplification circuit. In this conventional example, in Fig. 0, which describes a case where three video amplifiers are provided for three RGB signals,
lr, Ig, lb are R1G, B signal input terminal, 2r respectively
, 2g, 2b are respectively R1G, B video amplifier, 3r, 3g
, 3b are R1G and B signal output terminals, R1, R2, R
3, R4 is a resistor, and VRl, VH2, and VH2 are variable resistors. Furthermore, 4r, 4g, and 4b are R and G, respectively.
B映像増幅器2r、2g、2bの利得制御電圧入力端子
である。This is a gain control voltage input terminal for the B video amplifiers 2r, 2g, and 2b.
次に動作について説明する。R,G、B信号入力端子1
r、Ig、lbに到来したR、G、B信号は各々映像増
幅器2r、2g、2bにて増幅され、各々の出力端子3
r、3g、3bに出力信号として得られる。この映像増
幅器2r、2g、2bの利得は、利得制御電圧入力端子
4 r + 4 g +4bの直流電圧を変化するこ
とによって、制御できる。Next, the operation will be explained. R, G, B signal input terminal 1
The R, G, and B signals arriving at r, Ig, and lb are amplified by video amplifiers 2r, 2g, and 2b, respectively, and sent to the respective output terminals 3.
r, 3g, and 3b as output signals. The gains of the video amplifiers 2r, 2g, and 2b can be controlled by changing the DC voltage of the gain control voltage input terminal 4r+4g+4b.
映像増幅器2r、2g、2bの利得制御は、可変抵抗器
VRIによって、同時に利得制御電圧入力端子4r、4
g、4bの直流電圧を変化させることによって行ってい
る。Gain control of the video amplifiers 2r, 2g, and 2b is performed by variable resistors VRI, and gain control voltage input terminals 4r, 4 at the same time.
This is done by changing the DC voltages of g and 4b.
ところで各映像増幅器の利得制御電圧の値と利得の変化
量とは、必ずしも同じでない。このため可変抵抗VR1
,抵抗R1,R4の分圧比によって決まる電圧を利得制
御電圧入力端子4rに印加した時のR映像増幅器2rの
利得と、他の映像増幅器2g、2bの利得とが同じにな
る様、可変抵抗VR2,VR3によって調整する。なお
抵抗R2、R3は、可変抵抗VR2,VR3(7)抵抗
値を変化させた時に、利得制御電圧入力端子4rの電圧
が変わらないようにするためのものである。However, the value of the gain control voltage and the amount of change in gain of each video amplifier are not necessarily the same. Therefore, variable resistor VR1
, the variable resistor VR2 is set so that the gain of the R video amplifier 2r and the gains of the other video amplifiers 2g and 2b are the same when a voltage determined by the voltage division ratio of the resistors R1 and R4 is applied to the gain control voltage input terminal 4r. , adjusted by VR3. Note that the resistors R2 and R3 are used to prevent the voltage at the gain control voltage input terminal 4r from changing when the resistance value of the variable resistors VR2 and VR3 (7) is changed.
従来の映像増幅器の利得制御回路は、以上のように構成
されているので、あるレベルの利得の時は、補助の可変
抵抗器によって3つの映像増幅器の利得を同じにする事
ができるが、利得を変化させた時は、必ずしも3つの映
像増幅器の利得が同じように変化しない等の問題があっ
た。Conventional video amplifier gain control circuits are configured as described above, so when the gain is at a certain level, the gains of the three video amplifiers can be made the same using an auxiliary variable resistor, but the gain When changing , there was a problem that the gains of the three video amplifiers did not necessarily change in the same way.
この発明は、上記のような問題点を解消するためになさ
れたもので、複数個の映像増幅器の利得を同時に変化さ
せた時、全ての映像増幅器の利得変化量を常に同じ値と
することができる映像増幅器の利得制御回路を得ること
を目的とする。This invention was made to solve the above-mentioned problems, and when the gains of multiple video amplifiers are changed at the same time, it is not possible to always make the amount of gain change of all the video amplifiers the same value. The purpose of this study is to obtain a gain control circuit for a video amplifier that can be used.
該重畳信号を映像増幅器により増幅した後抜き取り、そ
の抜取信号同志のレベルを比較し、その差に応じて各々
の映像増幅器の利得が同じになるように制御するように
構成したものである。The superimposed signal is amplified by a video amplifier and then extracted, the levels of the extracted signals are compared, and the gain of each video amplifier is controlled to be the same according to the difference.
この発明においては、利得制御回路は、水平帰線消去期
間に重畳した信号のレベル差に応じて、各々の映像増幅
器の利得が同じになるように機能するので、各々の映像
増幅器の利得は常に等しくなる。In this invention, the gain control circuit functions so that the gain of each video amplifier becomes the same according to the level difference of the signals superimposed during the horizontal blanking period, so the gain of each video amplifier always remains the same. be equal.
以下、この発明の一実施例を図について説明する。第1
図は本発明の一実施例による映像増幅器の利得制御回路
を示し、図において、tr、tg。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a gain control circuit of a video amplifier according to an embodiment of the present invention, and in the figure, tr, tg.
1bは各々R−G−B信号入力端子、2r、2g。1b are R-G-B signal input terminals, 2r and 2g.
2bは各々R−G−B映像増幅器、3r、3g。2b is an R-G-B video amplifier, 3r and 3g.
3bは、R−G−B信号出力端子、4r、4g。3b is an R-G-B signal output terminal, 4r and 4g.
4bは各々の映像増幅器2r、2、g、2bの利得制御
電圧入力端子である。またVRIは可変抵抗器であり、
前記利得制御電圧入力端子4r、4g。4b is a gain control voltage input terminal of each of the video amplifiers 2r, 2, g, and 2b. Also, VRI is a variable resistor,
The gain control voltage input terminals 4r, 4g.
4bの電圧を変化させることによって、映像増幅器2r
、2g、2bの利得を制御している。R1゜R2,R3
は利得制御電圧入力端子4r、4g。By changing the voltage of 4b, the video amplifier 2r
, 2g, and 2b are controlled. R1゜R2, R3
are gain control voltage input terminals 4r and 4g.
4bの電圧が互いに影響を及ぼさないように挿入された
抵抗器である。This is a resistor inserted so that the voltages of 4b do not affect each other.
また5は重畳信号及び重畳信号抜き取りパルスの入力端
子、6r、6g、6bは重畳信号抜き取り回路、7g、
7bは信号レベル比較回路、8g。Further, 5 is an input terminal for a superimposed signal and a superimposed signal extraction pulse, 6r, 6g, and 6b are superimposed signal extraction circuits, 7g,
7b is a signal level comparison circuit, and 8g.
8bは利得制御電圧発生回路、R4,R5は抵抗器、9
r、9g、9bは信号重畳回路である。8b is a gain control voltage generation circuit, R4 and R5 are resistors, 9
r, 9g, and 9b are signal superimposition circuits.
従来例で説明した様に、可変抵抗器VRIによって設定
された同一の電圧が、映像増幅器2r、2g、2bの利
得制御電圧端子4r、4g、4bに印加されるが、映像
増幅器2r、2g、2t)はその利得にばらつきがある
為、出力の信号レベルは必ずしも同一でない。そこで水
平帰線消去期間にR,G、B映像信号に重畳した信号を
増幅後抜き取り、該抜き取った信号同志のレベルを比較
し、その差に応じて映像増幅器2r、2g、2bの利得
を制御することが本発明の原理である。As explained in the conventional example, the same voltage set by the variable resistor VRI is applied to the gain control voltage terminals 4r, 4g, 4b of the video amplifiers 2r, 2g, 2b. 2t) has variations in its gain, so the output signal levels are not necessarily the same. Therefore, the signals superimposed on the R, G, and B video signals during the horizontal blanking period are amplified and extracted, the levels of the extracted signals are compared, and the gains of the video amplifiers 2r, 2g, and 2b are controlled according to the difference. This is the principle of the present invention.
以下、この発明の一実施例の動作について説明する。R
,G、B信号入力端子1r、Ig、lbに到来した信号
に、重畳信号及び重畳信号抜き取りパルスの入力端子5
からの重畳信号を信号重畳回路9r、9g、9bにて、
R,G、 B信号の水平帰線消去期間に重畳する。この
水平帰線消去期間に一定レベルの信号が重畳されたR
−c −BH8号は、映像増幅器2r、2g、2bによ
って増幅され、重畳信号抜き取り回路6r、6g、6b
によって、水平帰線消去期間に重畳された重畳信号のみ
が抜き取られる。この抜き取られた信号の内、例えばR
信号に重畳された信号を基準とし、G信号及びB信号の
重畳信号のレベルを、信号レベル比較回路7g、7bで
比較する。基準となるR信号に重畳された信号とその信
号に重畳された信号との間にレベル差があれば、利得制
御電圧発生回路8g、8bの出力電圧は、信号レベル比
較回路7.7bの出力信号によってホールドされた信号
と可変抵抗器VRIによって設定された電圧が加算され
た値となる。この利得側?II+電圧発生回路8g、1
3bの出力電圧は、抵抗R4,R5を介して、利得制御
電圧端子4g、4bに印加される。この印加された電圧
によって、映像増幅器2g、2bの利得は、前記水平帰
線消去期間に重畳された信号のレベル差が零となる様に
変化する。The operation of one embodiment of the present invention will be described below. R
, G, B signal input terminals 1r, Ig, lb, input terminal 5 for superimposed signal and superimposed signal extraction pulse
The superimposed signals from the signal superimposing circuits 9r, 9g, 9b,
Superimposed on the horizontal blanking period of R, G, and B signals. A signal of a certain level is superimposed during this horizontal blanking period.
-c-BH8 is amplified by video amplifiers 2r, 2g, 2b, and superimposed signal extraction circuits 6r, 6g, 6b.
Accordingly, only the superimposed signal superimposed during the horizontal blanking period is extracted. Among these extracted signals, for example, R
Using the signal superimposed on the signal as a reference, the levels of the superimposed signals of the G signal and the B signal are compared by signal level comparison circuits 7g and 7b. If there is a level difference between the signal superimposed on the reference R signal and the signal superimposed on that signal, the output voltage of the gain control voltage generation circuits 8g and 8b will be the output of the signal level comparison circuit 7.7b. The value is the sum of the signal held by the signal and the voltage set by the variable resistor VRI. This gain side? II + voltage generation circuit 8g, 1
The output voltage of 3b is applied to gain control voltage terminals 4g and 4b via resistors R4 and R5. The applied voltage changes the gains of the video amplifiers 2g and 2b so that the level difference between the signals superimposed during the horizontal blanking period becomes zero.
即ち映像増幅2g、2bの利得は、常に映像増幅器2r
の利得と同じになる。That is, the gain of the video amplifiers 2g and 2b is always the same as that of the video amplifier 2r.
will be the same as the gain of
以上のように、この発明に係る映像増幅器の利得制御回
路によれば、複数個の映像増幅器の利得制御を行う時、
各々の人力映像信号の水平帰線消去期間に振幅が一定の
信号を重畳し、増幅後これ等の重畳信号を抜き取り、そ
れ等のレベル差を比較して得た差電圧を、前記映像増幅
器にフィードバックするように構成されているので、複
数個の映像増幅器の利得を常に同じにすることができる
という効果がある。As described above, according to the gain control circuit for a video amplifier according to the present invention, when performing gain control of a plurality of video amplifiers,
A signal with a constant amplitude is superimposed on the horizontal blanking period of each human-powered video signal, and after amplification, these superimposed signals are extracted, and the difference voltage obtained by comparing the level differences between them is sent to the video amplifier. Since it is configured to provide feedback, it has the advantage that the gains of a plurality of video amplifiers can always be made the same.
第1図はこの発明の一実施例による映像増幅器の利得制
御回路の構成図、第2図は従来回路の構成図である。
図において、lr、Ig、lbはR,G、 B信号入力
端子、2r、2g、2bはR,G、 B映像増幅器、3
r、3g、3bはR,G、B信号出力端子、4r、4g
、4bは利得制御電圧入力端子、5は重畳信号及び重畳
信号抜き取りパルスの入力端子、6r、6g、6bは重
畳信号抜き取り回路(信号抜取手段)、7g、7bは信
号レベル比較回路(レベル差検出手段)、8g、8bは
利得制御電圧発生回路(利得制御手段)、9r、9g。
9bは信号重畳回路(信号重畳手段”) 、VRI。
VR2,VR3は可変抵抗器、R1,R2,R3゜R4
,R5は抵抗器である。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a block diagram of a gain control circuit for a video amplifier according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional circuit. In the figure, lr, Ig, and lb are R, G, and B signal input terminals, 2r, 2g, and 2b are R, G, and B video amplifiers, and 3
r, 3g, 3b are R, G, B signal output terminals, 4r, 4g
, 4b is a gain control voltage input terminal, 5 is an input terminal for a superimposed signal and a superimposed signal extraction pulse, 6r, 6g, and 6b are superimposed signal extraction circuits (signal extraction means), and 7g and 7b are signal level comparison circuits (level difference detection 8g and 8b are gain control voltage generation circuits (gain control means), 9r and 9g. 9b is a signal superimposition circuit (signal superposition means), VRI. VR2 and VR3 are variable resistors, R1, R2, R3゜R4
, R5 are resistors. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
増幅器の利得制御回路において、 各々の入力映像信号の水平帰線消去期間に振幅が等しい
信号を重畳する信号重畳手段と、 前記重畳信号の映像増幅器による増幅信号より、前記水
平帰線消去期間に重畳した信号を抜き取る信号抜取手段
と、 該抜き取った各々の信号のレベルを比較しその差を検出
するレベル差検出手段と、 該検出したレベル差に応じて各々の映像増幅器の利得を
制御する利得制御手段とを備え、 各々の映像増幅器の利得を同時に変化させた時その変化
量が常に同じであることを特徴とする映像増幅器の利得
制御回路。(1) In a gain control circuit of a video amplifier that changes the gain of a plurality of video signals simultaneously, a signal superimposition means for superimposing a signal having the same amplitude on a horizontal blanking period of each input video signal; Signal extraction means for extracting the signal superimposed during the horizontal blanking period from the amplified signal by the video amplifier; Level difference detection means for comparing the levels of each of the extracted signals and detecting the difference; and the detected level. gain control means for controlling the gain of each video amplifier according to the difference, and the amount of change is always the same when the gain of each video amplifier is changed simultaneously. circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61031062A JPS62188582A (en) | 1986-02-14 | 1986-02-14 | Gain control circuit for video frequency amplifier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61031062A JPS62188582A (en) | 1986-02-14 | 1986-02-14 | Gain control circuit for video frequency amplifier |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62188582A true JPS62188582A (en) | 1987-08-18 |
Family
ID=12320981
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61031062A Pending JPS62188582A (en) | 1986-02-14 | 1986-02-14 | Gain control circuit for video frequency amplifier |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62188582A (en) |
-
1986
- 1986-02-14 JP JP61031062A patent/JPS62188582A/en active Pending
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