JPS62188347A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPS62188347A
JPS62188347A JP61029087A JP2908786A JPS62188347A JP S62188347 A JPS62188347 A JP S62188347A JP 61029087 A JP61029087 A JP 61029087A JP 2908786 A JP2908786 A JP 2908786A JP S62188347 A JPS62188347 A JP S62188347A
Authority
JP
Japan
Prior art keywords
semiconductor device
resin
silicon
gold
elastic material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61029087A
Other languages
Japanese (ja)
Inventor
Koji Nose
幸之 野世
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP61029087A priority Critical patent/JPS62188347A/en
Publication of JPS62188347A publication Critical patent/JPS62188347A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To disperse the stress resulting from the contraction due to the hardening of sealing resin and the drop in temperature, to reduce the fluctuations in characteristics of a semiconductor device, and to prevent the protective film on the surface from breakdown by a method wherein the surface and the side face of the semiconductor device adhered to a die-pad are coated with the elastic material such as silicon resin, and resin is sealed thereon. CONSTITUTION:After silver or gold-plated layer 6 has been formed on the bottom face 5 of a die-pad 3 and on the part corresponding to the tip part of an inner lead 4, a press working is performed. Then, the semiconductor device 7, consisting of silicon and other compound, is adhered to the bottom face 5 of the die-pad 3 with silver paste and by performing a gold-silicon eutectic method. Then, the terminal 8 formed on the surface of the semiconductor device 7 and the metal-plated layer 6 of the inner lead 4 are connected using the metal fine wire 9 consisting of the alloy of gold, silver, copper and aluminum. Subsequently, a liquid elastic material 10, having elasticity after hardened like silicon resin, is dripped on the semiconductor device 7 in such a manner that the material 10 does not overflow a partition wall 2 and the entire semiconductor device 7 is buried. The above- mentioned liquid elastic material 10 is turned to jelly-formed elastic resin 10 when hardened. Then, the above-mentioned material is charged in the cavity of package molding metal, fused novolac epoxy resin 11 and the like is filled in, and it is hardened.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、半導体集積回路を保護する半導体パッケージ
に関し、特に樹脂封止型の高信頼性半導体パッケージに
関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor package for protecting a semiconductor integrated circuit, and particularly to a highly reliable resin-sealed semiconductor package.

（従来の技術） 近年、半導体装置は、多機能を１個の装置に取り入れる
ために、パターンの微細化と並行して、大面積化が進ん
でいる。(Prior Art) In recent years, in order to incorporate multiple functions into a single device, the area of semiconductor devices has been increasing in parallel with the miniaturization of patterns.

このような大面積半導体装置の樹脂封止型半導体パッケ
ージを得るには、まず、鉄−ニッケル系合金にッケル４
２重量パーセント）や銅系合金からなるリードフレーム
のダイパッドに、金−硅素共晶や、エポキシ樹脂又はポ
リイミド梗脂中に銀粉末を混合したペーストで半導体装
置を固着する。In order to obtain a resin-sealed semiconductor package for such a large-area semiconductor device, first, an iron-nickel alloy is coated with Nickel 4.
A semiconductor device is fixed to a die pad of a lead frame made of a copper-based alloy (2% by weight) or a copper-based alloy using a paste made of gold-silicon eutectic, epoxy resin, or polyimide starch mixed with silver powder.

次に、半導体装置の表面に設けられたアルミニウムやア
ルミニウムー硅素合金等で構成された端子と、リードフ
レームのインナリードの先端に形成された銀や金等の薄
いメッキ層とを、金、銀、銅。Next, the terminals made of aluminum, aluminum-silicon alloy, etc. provided on the surface of the semiconductor device and the thin plating layer of silver, gold, etc. formed on the tips of the inner leads of the lead frame are coated with gold, silver, etc. ,copper.

アルミニウム等の金属細線を用い超音波振動法や熱圧着
法により接続する。次に、表面温度が１６０℃ないし１
９０℃に維持されたパッケージ成形用金型のキャビティ
に装填し、溶融状のノボラック系エポキシ樹脂を注入し
た後、放冷し半導体装置と、金属細線、リードフレーム
の一部とを樹脂中に封じ込める。Connections are made using ultrasonic vibration or thermocompression bonding using thin metal wires such as aluminum. Next, the surface temperature is between 160℃ and 1
After filling the cavity of a package mold maintained at 90°C and injecting molten novolac epoxy resin, it is left to cool and the semiconductor device, thin metal wire, and part of the lead frame are sealed in the resin. .

さらに、樹脂の外部のリードフレームに表面処理を施し
、さらに不要分の切断分離、曲げ等の加工、樹脂表面へ
の表示刻印の工程を経て樹脂封止型半導体パッケージが
完成する。Furthermore, a resin-sealed semiconductor package is completed by performing surface treatment on the lead frame outside the resin, and further processing such as cutting and separating unnecessary parts, bending, etc., and marking an indication on the resin surface.

（発明が解決しようとする問題点） しかしながら、上記の構成では、高温の成形用金型に注
入された溶融状の樹脂が硬化する時の収縮と、さらに常
温に戻る時の収縮とによって、硅素からなる半導体装置
に圧縮、剪断等の応力が加えられる。その結果、硅素単
結晶にピエゾ効果が生じ、半導体装置の表面に形成され
た各素子の特性に変動を生じさせるという問題があった
。(Problem to be Solved by the Invention) However, in the above configuration, the silicon shrinks due to shrinkage when the molten resin injected into the high-temperature mold hardens and further shrinks when the temperature returns to room temperature. Stresses such as compression and shearing are applied to a semiconductor device consisting of As a result, a piezoelectric effect occurs in the silicon single crystal, causing a problem of variations in the characteristics of each element formed on the surface of the semiconductor device.

この変動量は、半導体装置の大きさや半導体装置上の位
置、パッケージ用樹脂の種類、パッケージの形状等で異
なるため、これらの要因を考慮して樹脂封止型パッケー
ジを正確に設計することは難しいという問題があった。This amount of variation varies depending on the size of the semiconductor device, its position on the semiconductor device, the type of packaging resin, the shape of the package, etc., so it is difficult to accurately design a resin-sealed package by taking these factors into account. There was a problem.

さらに、半導体装置の表面と樹脂との界面で生ずる剪断
応力は、半導体装置の表面に形成されている金属配線微
細パターンに移動を生じさせ、同時に表面保護膜を破壊
するという問題があった。Furthermore, there is a problem in that the shear stress generated at the interface between the surface of the semiconductor device and the resin causes movement of the fine metal wiring pattern formed on the surface of the semiconductor device, and at the same time destroys the surface protective film.

さらに、これらはパターンくずれや耐湿性紙下等の原因
となるという問題もあった。Furthermore, there are also problems in that these may cause pattern deformation and moisture-resistant paper defects.

本発明は上記の問題点を解決するもので、半導体装置に
応力を加えることのない半導体パッケージを提供するも
のである。The present invention solves the above problems and provides a semiconductor package that does not apply stress to a semiconductor device.

（問題点を解決するための手段） 上記の問題点を解決するために、本発明は、ダイパッド
上に固着された半導体装置の表面および側面をシリコー
ン樹脂のような弾性材料で覆い、その上を樹脂で封止す
るものである。(Means for Solving the Problems) In order to solve the above problems, the present invention covers the surface and side surfaces of a semiconductor device fixed on a die pad with an elastic material such as silicone resin. It is sealed with resin.

（作　用） 半導体装置の表面や側面をシリコーン樹脂のような弾性
材料で覆い、封止樹脂と直接接触しないので、封止樹脂
の硬化および温度降下による収縮によって半導体装置に
加えられる応力が分散され、さらに、半導体装着に表面
に発生する剪断応力を大幅に低減することができる。(Function) Since the surface and side surfaces of the semiconductor device are covered with an elastic material such as silicone resin and do not come into direct contact with the encapsulating resin, the stress applied to the semiconductor device due to curing of the encapsulating resin and shrinkage due to temperature drop is dispersed. Furthermore, the shear stress generated on the surface of semiconductor mounting can be significantly reduced.

（実施例） 本発明の一実施例について、樹脂封止型デュアルインラ
インパッケージを例として第１図および第２図により説
明する。(Example) An example of the present invention will be described with reference to FIGS. 1 and 2, taking a resin-sealed dual in-line package as an example.

第１図（Ａ）ないしくＥ）の５面の断面図は、本発明に
よる半導体パッケージを得る工程順序を示し、第２図の
斜視断面図はその内部構造を示したものである。The 5-sided sectional views in FIGS. 1A to 1E show the sequence of steps for obtaining a semiconductor package according to the present invention, and the perspective sectional view in FIG. 2 shows its internal structure.

第２図に示すように、リードフレームは、鉄−ニッケル
合金にッケル４２重量パーセント）の薄板に、連結梁１
で支えられた、四方に高さが０．２ｍｍないし０　、５
＋ｎｍの仕切り壁２がプレス成形されたダイパッド３と
、このダイパッド３に向って四方から延びるように配置
したインナリード４とをプレス成形したものである。As shown in Figure 2, the lead frame consists of a thin plate of iron-nickel alloy (42% by weight) with connecting beams
0.2 mm to 0.5 mm in height on all sides
A die pad 3 having a +nm partition wall 2 press-molded, and inner leads 4 arranged so as to extend from all sides toward the die pad 3 are press-molded.

第１図（Ａ）に示すように、まず、上記のプレス成形に
先立って、ダイパッド３の底面５およびインナリード４
の先端部に相当する部分に厚さ１μｍないし３μｍの銀
又は金のメッキ層６を形成した後、プレス加工を施す。As shown in FIG. 1(A), first, prior to the above press forming, the bottom surface 5 of the die pad 3 and the inner lead 4 are
After forming a silver or gold plating layer 6 with a thickness of 1 μm to 3 μm on a portion corresponding to the tip, press working is performed.

次に、第１図（Ｂ）に示すように、硅素やその他の化合
物からなる半導体装置７を、金−硅素共晶法や銀ペース
トで、ダイパッド３の底面５に固着する。上記の金−硅
素共晶法の場合は、温度３８０℃ないし５５０℃の低酸
素濃度雰囲気中で、加熱して固着する。Next, as shown in FIG. 1B, a semiconductor device 7 made of silicon or other compound is fixed to the bottom surface 5 of the die pad 3 using the gold-silicon eutectic method or silver paste. In the case of the above-mentioned gold-silicon eutectic method, the film is fixed by heating in a low oxygen concentration atmosphere at a temperature of 380°C to 550°C.

次に、第１図（Ｃ）に示すように、半導体装置７の表面
に形成された端子８と、インナリード４のメッキ層６の
間を、金や銀、銅、アルミニウム系の合金からなる金属
細線９を用い、室温から温度４５０℃の範囲で、超音波
振動法や熱圧着法により接続する。Next, as shown in FIG. 1(C), between the terminal 8 formed on the surface of the semiconductor device 7 and the plating layer 6 of the inner lead 4, a layer made of gold, silver, copper, or aluminum alloy is formed. Connection is made using a thin metal wire 9 at a temperature ranging from room temperature to 450° C. by ultrasonic vibration method or thermocompression bonding method.

次に、第１図（Ｄ）に示すように、シリコーン樹脂のよ
うに硬化後に弾性を有する液状の弾性材料１０を半導体
装置７の上に滴下し、仕切り壁２を越えず、しかも半導
体装置７全体が埋没するようにする。硬化するとゼリー
状の弾性樹脂１０となる。Next, as shown in FIG. 1(D), a liquid elastic material 10, such as silicone resin, which has elasticity after hardening, is dropped onto the semiconductor device 7 so that it does not cross the partition wall 2, and the semiconductor device 7 Make sure the whole thing is buried. When cured, it becomes a jelly-like elastic resin 10.

次に、パッケージ成形金属（図示せず）のキャビティに
装填し、溶融したノボラック系のエポキシ樹脂１１等を
注入し硬化すると、第１図（Ｅ）に示すような半導体パ
ッケージ】２が得られる。Next, the package is loaded into a cavity of a molded metal package (not shown), and a molten novolac epoxy resin 11 or the like is injected and hardened to obtain a semiconductor package 2 as shown in FIG. 1(E).

その後、インナリード４の切断、折曲げ工程を経て、第
２図に示す半導体パッケージ１２が得られる。Thereafter, the inner lead 4 is cut and bent, and the semiconductor package 12 shown in FIG. 2 is obtained.

（発明の効果） 以上説明したように、本発明によれば、半導体装置の表
面と側面をシリコーン樹脂のような弾性樹脂で覆い、半
導体装置が直接封止樹脂と接触するのを妨げることによ
って、封止樹脂の硬化と温度の降下による収縮に基因す
る応力を分散し半導体装置に加えられて生ずる局部集中
応力の発生を防止し、その特性の変動を大幅に減少する
。(Effects of the Invention) As explained above, according to the present invention, by covering the surface and side surfaces of the semiconductor device with an elastic resin such as silicone resin and preventing the semiconductor device from coming into direct contact with the sealing resin, It disperses stress caused by shrinkage due to hardening of the sealing resin and temperature drop, prevents the occurrence of locally concentrated stress that is caused by being applied to semiconductor devices, and significantly reduces fluctuations in their characteristics.

また、半導体装置の表面と、封止樹脂は直接接触しない
ので、剪断応力による半導体装置の表面に形成された金
属配線パターンの移動と、それに伴う表面保護膜の破壊
が防止でき、特性変動も防止できる。In addition, since the surface of the semiconductor device and the encapsulating resin do not come into direct contact, it is possible to prevent the movement of the metal wiring pattern formed on the surface of the semiconductor device due to shear stress and the resulting destruction of the surface protective film, and also prevent changes in characteristics. can.

さらに、半導体装置の角や縁が弾性樹脂で覆われるため
、熱サイクル等に基因する封止樹脂の割れの発生がなく
なる。Furthermore, since the corners and edges of the semiconductor device are covered with the elastic resin, cracking of the sealing resin due to thermal cycles and the like is eliminated.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（Ａ）ないしくＥ）は本発明による半導体パッケ
ージの製造工程を示す断面図、第２図はその半導体パッ
ケージの斜視断面図である。 １・・・連結梁、　２・・・仕切り壁、　３・・・ダイ
パッド、　　４・・・インナリード、　　５・・・底面
、６・・・メッキ層、　　７・・・半導体装置、　８・
・・端子、　９・・・金属細線、　１０・・・弾性材料
、１１・・・封止樹脂、　１２・・・半導体パッケージ
。FIGS. 1A to 1E are cross-sectional views showing the manufacturing process of a semiconductor package according to the present invention, and FIG. 2 is a perspective cross-sectional view of the semiconductor package. DESCRIPTION OF SYMBOLS 1... Connecting beam, 2... Partition wall, 3... Die pad, 4... Inner lead, 5... Bottom surface, 6... Plating layer, 7... Semiconductor device, 8...
...terminal, 9...metal thin wire, 10...elastic material, 11...sealing resin, 12...semiconductor package.

Claims (4)

【特許請求の範囲】[Claims] （１）少なくとも、ダイパッドの上に固着された半導体
装置と、その表面と側面を覆う弾性材料と、上記のダイ
パッド、半導体装置および弾性材料を内包する封止樹脂
とからなる半導体パッケージ。(1) A semiconductor package comprising at least a semiconductor device fixed on a die pad, an elastic material covering the surface and side surfaces of the semiconductor device, and a sealing resin containing the die pad, the semiconductor device, and the elastic material. （２）ダイパッドが半導体装置の固着面と、固着面の周
縁に形成した仕切り壁とから形成され、上記の仕切り壁
と半導体装置の側面との間に弾性材料が充填された特許
請求の範囲第（１）項記載の半導体パッケージ。(2) The die pad is formed from a fixed surface of a semiconductor device and a partition wall formed around the periphery of the fixed surface, and an elastic material is filled between the partition wall and the side surface of the semiconductor device. The semiconductor package described in (1). （３）ダイパッドがリードフレームと同一材料から一体
で形成された特許請求の範囲第（１）項又は第（２）項
記載の半導体パッケージ。(3) The semiconductor package according to claim (1) or (2), wherein the die pad and the lead frame are integrally formed from the same material. （４）ダイパッドがリードフレームと別体に成形され、
リードフレームに接続された特許請求の範囲第（１）項
又は第（２）項記載の半導体パッケージ。(4) The die pad is molded separately from the lead frame,
A semiconductor package according to claim (1) or (2) connected to a lead frame.
JP61029087A 1986-02-14 1986-02-14 Semiconductor package Pending JPS62188347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61029087A JPS62188347A (en) 1986-02-14 1986-02-14 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61029087A JPS62188347A (en) 1986-02-14 1986-02-14 Semiconductor package

Publications (1)

Publication Number Publication Date
JPS62188347A true JPS62188347A (en) 1987-08-17

Family

ID=12266567

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61029087A Pending JPS62188347A (en) 1986-02-14 1986-02-14 Semiconductor package

Country Status (1)

Country Link
JP (1) JPS62188347A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014027266A (en) * 2012-06-20 2014-02-06 Asahi Kasei Electronics Co Ltd Semiconductor package and manufacturing method of the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014027266A (en) * 2012-06-20 2014-02-06 Asahi Kasei Electronics Co Ltd Semiconductor package and manufacturing method of the same

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