JPS62186611A - Phase comparison circuit - Google Patents

Abstract

PURPOSE:To attain the phase comparison even when one of the rise and fall characteristics of a data signal is not steep by applying phase comparison to both the non-inverting and inverting phases of the data signal. CONSTITUTION:A signal (h) is produced at a Q output of a FF 10 at the rise of a data signal (a) and signals (i) and the inverse of (i) are caused in Q and Q outputs of the FF 11 in response to a clock pulse (b). The signals (h) and the inverse of (i) are inputted to an AND circuit 13 and its output signal (k) is a basic pulse in obtaining a phase difference between the signal (a) and the pulse (b). Further, the signal (i) and the signal the inverse of b from the pulse (b) via an inverter 12 enter and AND circuit 14 an its output signal (j) goes to a reference pulse. Then when a signal (l) is caused to the Q output of the FF 16 at the fall (signal the inverse of (a) of the signal (a), signals (m), the inverse of (m) are caused at Q,Q outputs of the FF 17. The signals (n), (o) from AND circuits 18, 19 correspond to signals j, k, the signal (o) is a basic pulse in obtaining the phase and the signal (n) is a reference pulse.

Description

[Detailed description of the invention] [Background and purpose of the invention] The present invention relates to a phase comparator circuit.

A phase comparison circuit compares the phases of two signals, and examples of conventional phase comparison circuits include those shown in FIGS. 3 to 6.

Figure 3 shows flip-flops 1 and 2 and exclusive OR circuit 3.
, 4 to compare the phases of the data signal a and the clock pulse b using the output signals r and ri.

The relationship between the signals a to g is as shown in the operation explanatory diagram of FIG. 4. When data signal a and clock pulse b are input, clock pulse b is output from the output Q of flip-flop 1.
The rising time t! The signal d is generated after the operation delay time t1 of the flip-flop 1. Since the signal d and the opposite phase signal C of the clock pulse are input to the flip-flop 2, the signal e is input from the output Q of the flip-flop 2 to the rising time t2 of the clock pulse C at an interval of 11 hours in the same way as the signal @d. arise. Since the signal d and the signal e are input to the exclusive OR circuit 3, the signal [ is generated from its output. The pulse width of signal f is the same as that of signal d and signal e at time t.
1. Since both are one hour later than t2, they are equal to the pulse width of clock pulse C and serve as the reference pulse when calculating the phase. The data signal a and the signal are input to an exclusive OR circuit 4, and an output signal g is generated.

The difference in pulse width between signal q and signal f represents the phase difference between data signal a and clock pulse b. In this case, signal f can be used as a reference, but signal g has the above-mentioned delay. Since time t1 is included, the phase difference obtained from signal 9 and signal f will have an error of 11 hours.

Therefore, when using the circuit of FIG. 3 in a PLL (phase-locked loop) circuit, for example, t' in FIG.
There is a tendency for a steady phase error as shown in 1 to occur.

FIG. 5 shows a phase comparator circuit that is an improved version of the circuit shown in FIG.

The relationship between the signals a to g is as shown in the operation explanatory diagram of FIG.

Data signal a is edge trigger type flip-flop 5
When inputted below the trigger terminal of the flip-flop 5, a signal is generated from the output terminal Q of the flip-flop 5 12 hours later than the time to. When this signal is inputted to the D terminal of the edge trigger type flip-flop 6 and the clock pulse b is inputted to the bottom of the trigger terminal, a signal i is generated from the output Q of the flip 70 knob 6 by 13 hours after time t1. A signal i is generated from the output Q. When the signal i and the clock pulse b passed through the inverter 7 are input to the AND circuit 8, the reference signal pulse r is generated from the output.The pulse width of the signal f is as shown in the figure. It is equal to the pulse width of the off-time of pulse b. Signal RI and signal i are input to an AND circuit 9, which outputs phase signal pulse 9. Signal RI and signal i are from time 0 and t, respectively, t2 and 13. Although it is delayed, since t 2 - t 3 can be set, the pulse width of the signal Q can be used as the basic pulse when calculating the phase of the data signal a and the clock pulse b. Therefore, the phase signal pulse 9 and the reference signal The phase difference between the data signal a and the clock pulse b can be determined by the difference in the pulse width of the pulse f, and the steady phase error in the cases of FIGS. 3 and 4 can be eliminated.

However, in this circuit, the flip-flop 5 is operated using the rising characteristic of the data signal a, so when the rising characteristic of the data signal a is not steep, it becomes difficult to obtain an accurate phase. There is a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase comparison circuit that can perform phase comparison even if one of the rising and falling characteristics of a data signal is not steep.

[Summary of the Invention] The present invention includes a plurality of memory circuits and a plurality of logic circuits that operate using data signals and clock pulses as input signals, one of the logic circuits outputs a phase signal pulse, and the other outputs a reference signal pulse. A phase comparator circuit that outputs the data signal and compares the phase of the data signal and the clock pulse using these two output pulses includes a first storage circuit to which the data signal is input, and an output of the first storage circuit. a second memory circuit receiving the clock pulse;
a first AND circuit that receives as inputs one output of the storage circuit and the output of the first storage circuit, and receives as input the opposite phase pulse of the clock pulse and the other output of the second storage circuit. a second AND circuit, and a positive phase comparison section that operates at the rising edge of the data signal; and a third memory that receives an opposite phase signal of the data signal instead of the first memory circuit. circuit, and a third J5 and fourth AND circuit corresponding to the first and second AND circuits, forming a circuit configuration opposite to the positive phase comparator, and detecting a falling edge of the data signal. an anti-phase comparator that operates at a point in time, and a logical sum of the output of the first AND circuit of the positive phase comparator and the output of the third AND circuit of the anti-phase comparator. A logical sum of the output of the first logical sum circuit outputting the phase signal pulse, the second logical product circuit of the positive phase comparator, and the fourth logical product circuit of the antiphase comparator. and a second OR circuit outputting as the reference signal pulse, and one of the positive and negative phase comparators enables phase comparison, and one of the data signal rising and falling characteristics is steep. Even if this is not the case, the objective is to be achieved by ensuring that the phase comparison is performed stably.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the phase comparator circuit of the present invention.

In the figure, 10.11 and 16.17 are edge trigger type flip-flops, 12 is an inverter,
13.14Jy and i8.19 are AND circuits, respectively.
15.20 is an OR circuit.

A positive voltage Vcc of the power supply voltage is input to the D input terminal of the flip 70 tube 10, and a data signal a is input to the trigger input terminal. The output of the Q terminal of the flip-flop 10 is inputted to the D input terminal of the flip-flop 70 block 11, and the clock pulse b is inputted under the tri-terminal. Next, Vcc is input to the D input terminal of the flip-flop 16, and an opposite phase signal a of the data signal a is input to the trigger terminal J. Output 1 of the Q terminal of the flip 70 knob 16 is input to the D terminal of the flip 70 knob 17, and a clock pulse b is input under the trigger terminal.

The Q terminal output of the flip 70 tube 10 and the Q output i of the 7 lip 70 tube 11 are input to an AND circuit 13, and a signal k is taken out. The Q terminal output 1 of the flip-flop 11 and the output of the inverter 12 are input to the AND circuit 14, and a signal j is taken out from the output. The AND circuit 18 includes the Q terminal output m of the flip-flop 17 and the inverter 1.
2 is input, and an output signal n is taken out. AN
The output 1 of the flip-flop 16 and the Q output amount of the flip-flop 17 are input to the D circuit 19, and the output O is taken out.

The output of the AND circuit 13 and the output 0 of the AND circuit 19 are O.
It is input to the R circuit 15 and produces an output signal g.

The output j of the AND circuit 14 and the output n of the AND circuit 18 are O.
It is input to the R circuit 20 and produces an output r.

Signal Q and signal r, as in the case shown in Figs. 3 to 6, signal 9 serves as a basic phase signal pulse when determining the phase of data signal a and clock pulse b, and signal f serves as a reference signal pulse. Become.

A signal j and a signal n are sent to reset terminals R of flip-flops 10 and 16, and each flip-flop is reset by these signals.

The operation of the phase comparison circuit of this embodiment is as shown in FIG. t on the horizontal axis indicates time.

When data signal a is input at time Co, it is delayed by t1 hours from time to.
A signal is generated from the Q terminal of the When the clock pulse b is input, from the terminal Q of the flip-flop 11 and from the center,
At time t2 after time t1, signals: and i are generated at time 1, /.

Signal RI and signal 1 are input to AND circuit 13, which outputs signal k. Delay time t1 at signal and signal 1
．． Since t2 can be regarded as t1-t2, the signal becomes a basic pulse when determining the phase difference between the data signal a and the clock pulse b, like the signal g shown in FIGS. In addition, an inverter 12 for signal i and clock pulse b
Signal b1. It enters the tAND circuit 14 and generates a signal j. The pulse width of the signal j is equal to the pulse width of the clock pulse b due to the operation of the AND circuit 14. That is, signal j
can be used as a reference pulse like the signal shown in FIGS. 5 and 6.

Next, when the fall time of the data signal a, that is, the rise time t2 of the signal 1, is reached, the Q terminal of the flip 70 tube 16 produces the output signal 1 at a time t2', which is t'3 hours later than the time t2. When the signal 1 is generated, from the Q and Q terminals of the flip-flop 17, after a delay of t4 from time t3, at time t.
At 3', the signal run and i occur. Signal 1. When m, "i" is generated, the AND circuit 18.19 generates a signal n, a double signal. In this case, times t3 and t4 are t3-t, -
can be regarded as a double -12 signal, so the signal n and the double signal correspond to the signal j and the double signal, respectively, the signal O becomes the basic pulse when determining the phase, and the signal n becomes the reference pulse.

That is, in this embodiment, the signal k is the data signal a
This is the basic pulse when determining the phase of clock pulse b, and signal 0 is the basic pulse for the positive data signal. Further, the signal j and the signal n become basic pulses having the same pulse width as the clock pulse b.

Since the signal 0 is input to the OR circuit 15,
From the output, the phase signal pulse q can be extracted even if either signal or signal 0 is input, and since the signal @j and signal n are input to the OR circuit 20, the phase signal pulse q can be extracted from the output. In this case, the reference signal pulse f is generated regardless of which of the signals j and n is input, as shown in the figure.

Therefore, by comparing the pulse widths of the reference signal pulse f and the phase signal pulse g, the phase difference between the data signal a or τ and the clock pulse b can be determined.

In addition, in Fig. 1, 7 lips 70 lips 10 and 16
Although the D input terminal of is at a high potential, it can easily be set to a low level.

Also, the inverter 12 can be omitted if the anti-phase signal of the clock pulse b is used directly.

As described above, by using the embodiments of the present invention, (1) accurate phase difference between signals can be obtained, and PL
When applied to an L circuit, steady phase errors can be eliminated.

(2) When the above-mentioned steady phase error occurs, the rising points of the data signal and the clock pulse shift, making them susceptible to jitter (pulse fluctuations). Therefore, the present invention is suitable for data relay systems where jitter accumulates. Especially effective.

(a) Since the circuit operates using both the rising and falling characteristics of the data input signal, correct phase comparison operation can be obtained even if either characteristic deteriorates, so the restrictions on the data input signal pattern can be relaxed. be able to.

[Effects of the Invention] According to the present invention, it is possible to provide a phase comparison circuit that can perform phase comparison even if one of the rising and falling characteristics of a data signal is not steep.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of one embodiment of the phase comparator circuit of the present invention, FIG. 2 is an explanatory diagram of the operation of FIG. 1, FIGS. 3 and 5 are conventional phase comparator circuit diagrams, and FIGS. FIG. 6 is an explanatory diagram of the operations in FIGS. 3 and 5. 5.6, 10.11, 16, 17: Edge trigger type flip 70 tube, 7.12: Inverter, 8.9.13.14.18.19: AND circuit, 15.
20: OR circuit. Agent Patent Attorney Fujio Sato No. 2 Self-111t Part 3 Figure 4- Figure 1--→See also θ Ushimukai 5 Figure 6 Figure-11 sun time

Claims (1)

[Claims] (1) Equipped with a plurality of memory circuits and a plurality of logic circuits that operate using data signals and clock pulses as input signals, one of the logic circuits outputs a phase signal pulse, the other outputs a reference signal pulse, and these two A phase comparison circuit that compares the phases of the data signal and the clock pulse using two output pulses includes a first storage circuit that receives the data signal, and receives the output of the first storage circuit and the clock pulse as input. a second memory circuit; a first AND circuit that receives one output of the second memory circuit and the output of the first memory circuit; a second AND circuit that inputs the other output of the storage circuit, and operates at the rising edge of the data signal; The circuit comprises a third storage circuit inputting a signal, and third and fourth AND circuits corresponding to the first and second AND circuits, and has a circuit configuration identical to that of the positive phase comparator. and an anti-phase comparison section that operates at the falling edge of the data signal, the output of the first AND circuit of the positive phase comparison section and the third AND circuit of the anti-phase comparison section.
a first OR circuit that outputs the logical sum of the output of the AND circuit of the positive phase comparator as the phase signal pulse; an output of the second AND circuit of the positive phase comparator; a second logical sum circuit that outputs the logical sum with the output of the logical product circuit of No. 4 as the reference signal pulse;
A phase comparison circuit characterized in that phase comparison is made possible by one of the antiphase comparison sections.