JPS63193608A - Phase difference detecting circuit - Google Patents

Abstract

PURPOSE:To directly and accurately detect a phase difference as a digital value by outputting information from a gate only during a period corresponding to a phase difference between 1st and 2nd cock signals. CONSTITUTION:A reference clock signal phi1 is applied to a clock terminal L of a D-type FF 11, a clock signal phi2 to be an signal to be outputted is applied to a terminal D, an output Q' of a terminal is inputted to one input of an OR gate 12, and the signal phi2 is applied to the other input. The signal phi1, an information signal S and an output R' from the OR gate 12 are respectively inputted to a set input terminal ST, a terminal D and a reset terminal R of a latch circuit 13 with a resetting function and the information signal S is outputted from a terminal Q as a signal Q1 only by a period determined by the set signal phi1 and the reset signal R'. In such constitution, pulse signals proportional to a phase difference value between the signals phi1 and phi2 can be directly obtained.

Description

Detailed Description of the Invention [Objective of the Invention 1 (Field of Industrial Application) This invention is used in a PLL circuit that requires accurate phase difference detection results, such as a PLL circuit used in a hard disk controller. The present invention relates to a phase difference detection circuit.

(Conventional technology) FIG. 7 shows the configuration of a conventional phase difference detection circuit.

This phase difference detection circuit includes a multiplexer 1, a capacitor 2, and an A/D converter 3.

The multiplexer 1 is composed of an inverter 4.5, an AND gate 6.7, and an OR gate 8, and is supplied with φ1 as a reference clock signal and φ2 as a measured clock signal.

And the output from this multiplexer is capacitor 2
This charged analog voltage value is converted into a digital value by the A/D converter 3 and output.

FIG. 8 is a timing chart showing the operation of this phase difference detection circuit. As can be seen from this figure, the multiplexer 1 outputs the inverted clock signal φ2 when the reference clock signal φ1 is at the "'1" level, and always outputs the inverted clock signal φ2 when the reference clock signal φ1 is at the ii O++ level.
Outputs IOIT level. Therefore, the output of the multiplexer 1 becomes a signal corresponding to the phase difference between φ1 and φ2, and the capacitor 2 is charged by this signal.

Then, from the A/D converter 3, for example, as shown in the figure,
A number of pulse signals corresponding to this charge amount are output as phase difference detection signals.

However, in a phase difference detection circuit having such a configuration, the output level changes due to the influence of the temperature characteristics of the transistors constituting each gate circuit of the multiplexer 1, and the amount of charge in the capacitor 2 changes to the same phase difference. Very unstable with respect to quantity. For this reason, the number of pulse signals output from the A/D converter 3 may differ for the same amount of phase difference, making it impossible to perform accurate phase difference detection.

Furthermore, if we try to realize this circuit, a large pattern area is required to form the capacitor 2 and the complex A/D converter 3, so the chip area occupied by the phase difference detection circuit is extremely large. It becomes something big.

(Problems to be Solved by the Invention) The present invention was made in view of the above points, and it is difficult to accurately detect a phase difference with a conventional phase difference detection circuit. The present invention aims to improve the point that a large chip area is required to realize this, and to provide a phase difference detection circuit that has a simple configuration and can detect phase differences more accurately.

[Structure of the Invention] (Means and Effects for Solving Problems) In the phase difference detection circuit according to the present invention, first and second clock signals are supplied, and the circuit is synchronized with the second clock signal. and a second reset signal generated by latching the second clock signal based on the time point at which the first clock signal is generated. A generating means is supplied with digital data for phase difference detection, and is set to an output state in which the data is output at the time of generation of the first clock signal, and the output state is changed based on the output from the reset signal generating means. and gate means to be reset.

In the phase difference detection circuit having such a configuration, the first
Since the data is output from the gate means for a period corresponding to the phase difference between the clock signal and the second clock signal, the phase difference can be directly detected as a digital quantity. Therefore, it is possible to perform accurate phase difference detection with a simple configuration.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings. 1st
The figure shows the configuration of a phase difference detection circuit according to an embodiment of the present invention.

This phase difference detection circuit includes a D flip-flop 11, an OR gate 12, and a latch circuit 13 with reset. Clock input terminal OL of D flip-flop 11
A reference clock signal φ1 is supplied to the reference clock signal φ1, and a clock signal φ2 serving as a signal to be measured is supplied to its data input terminal. The output Q' from the Q output terminal of this D flip-flop 11 is supplied to one input of an OR gate 12, and the other input of this OR gate 12 is supplied with the clock signal φ2 to be measured. The reference clock signal φ1 is supplied to the set input terminal ST of the latch circuit with reset 13, the data signal S is supplied to the data input terminal, the output R' of the OR gate 12 is supplied to the reset input terminal R, and the set signal is supplied from the Q output terminal. Data signal S is output as signal Q1 only for a period determined by signal φ1 and reset signal R'.

Next, the operation of this phase difference detection circuit will be explained with reference to the timing chart of FIG.

Since the D flip-flop 11 works to maintain the level of φ2 at the rising edge of φ1, φ1 and φ2
When the relationship is as shown in the figure, the output Q' is as shown in the figure. Since Q' and φ2 are input to the OR gate 12, its output R' is in the form of the logical sum of φ2 and Q'.

Then, the output signal Q1 from the latch circuit with reset 13
is the data signal S itself if φ1 is “1” when R′ is “O”, and is the data signal S itself if φ1 is “0”
It becomes 1. Moreover, this output signal Q1 has R' of 1111
When it is +, it is always latched to 0''. That is, the data signal S is outputted from the Q output terminal of the latch circuit with reset 13 only for a period corresponding to the amount of delay phase difference of φ2 with respect to φ1.

As the data signal S, a lock pulse signal S1 as shown in FIG. 2(B) can be used. In this way, it is possible to directly generate a number of pulse signals proportional to the amount of phase difference between φ1 and φ2.

FIG. 3 shows another embodiment of the present invention, which has a configuration in which two phase difference detection circuits shown in FIG. 1 are combined.

That is, this phase difference detection circuit includes a first phase difference detection circuit section 14 made up of a D flip-flop 11a1, an OR gate 12a1, and a latch circuit with reset 13a, and a second phase difference detection circuit section 14 made up of a D flip-flop 11b1, an OR gate 12b1, and a latch circuit with reset 13b. It is composed of a phase difference detection circuit section 15.

The first phase difference detection circuit section 14 uses φ1 as a reference clock signal and φ2 as a measured clock signal, as in the circuit shown in FIG. 1, but the second phase difference detection circuit section 15 uses φ2 is a reference clock signal, and φ1 is a measured clock signal. Therefore, like the circuit shown in FIG. 1, the first phase difference detection circuit section 14 outputs the output signal Q1 only during the period corresponding to the delayed phase difference amount of φ2 with respect to φ1.
The output from the second phase difference detection circuit section 15 is as follows.
The data signal S is output as the output signal Q2 for a period corresponding to the amount of leading phase difference of φ2 with respect to φ1.

A timing chart of a phase difference detection circuit having such a configuration is shown in FIG. Here, an example is shown in which the "1" level signal is used as the signal S.

In this figure, Q JL is the second phase difference detection circuit section 1
The output of the D flip-flop 11b provided at Rn
Q2 represents the output of the OR gate 12b which serves as a reset signal, and Q2 represents the output signal from the latch circuit with reset 13b.

As can be seen from this figure, by combining the first phase difference detection circuit section 14 that uses φ1 as a reference clock signal and the second phase difference detection circuit section 15 that uses φ2 as a reference clock signal, φ1 It becomes possible to detect not only the lagging phase difference of φ2 with respect to φ2 but also the leading phase difference of φ2 with respect to φ1.

FIG. 5 shows another circuit configuration of the reset signal generating section consisting of the D flip-flop 11 and the OR gate 12 explained in FIG.

That is, in this reset signal generation circuit, the reference clock signal φ1 is supplied to one input of each of AND gates 21 and 22, and the measured clock signal φ2 is supplied to the other input of AND gate 21 and the clocked inverter 23. and the other input of the AND gate 22 via the inverter 24. The clocked inverter 23 is an AND gate 22
The drive is controlled by an output signal 3a from.

The output signal sb from the clocked inverter 23 is supplied to a latch circuit 25 composed of two inverters 25a and 125b, and the output signal SO from the latch circuit 25 is supplied to one input of an OR gate 26. The other input of this OR gate 26 has an AND gate 21
An output signal Sd from is supplied.

The output signal Se of this OR gate 26 becomes the reset signal R'.

A timing chart of this reset circuit is shown in FIG. As can be seen from this figure, the signal Se that becomes the reset signal
rises at the rising edge of φ2 and falls at the falling edge of φ1 when the clock signal to be measured is delayed in phase by 0° to 180° with respect to the reference clock signal φ1.

In addition, when φ2 is in an advanced phase from 1180° to 0° with respect to φ1, it rises at the timing of the first φ1 when it changes to an advanced phase, and continues until φ2 changes to a delayed phase.
″Hold the level.

Therefore, even if a reset circuit having such a configuration is used, the phase delay of φ2 with respect to φ1 can be detected in the same way as in FIG.

[Effects of the Invention] As described above, according to the present invention, it is possible to detect a phase difference using a digital amount instead of analog detection using a capacitor as in the past, and therefore, it is possible to detect a phase difference amount more accurately. becomes. Furthermore, since the phase difference detection signal is output as a digital signal, there is no need to provide an A/D converter, and the chip area can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram explaining a phase difference detection circuit according to an embodiment of the present invention, FIG. 2 is a timing chart explaining the operation of the phase difference detection circuit shown in FIG. 1, and FIG. 4 is a timing chart illustrating the operation of the phase difference detection circuit shown in FIG. 3, and FIG. 5 is a circuit diagram explaining the phase difference detection circuit according to another embodiment of the present invention. a circuit diagram illustrating another circuit configuration of a circuit section consisting of a D flip-flop and an OR gate provided in the circuit;
Figure 6 is a timing chart explaining the operation of a phase difference detection circuit using the circuit shown in Figure 5, Figure 7 is a circuit diagram explaining a conventional phase difference detection circuit, and Figure 8 is the same as Figure 7. 3 is a timing chart illustrating the operation of the illustrated phase difference detection circuit. 11...D flip-flop, 12...OR gate, 13...latch circuit with reset. Applicant's agent Patent attorney Takehiko Suzue Q $ 'a 'rx 6 ゞOjaku
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Claims (2)

[Claims] (1) first and second clock signals are supplied, a first reset signal is generated in synchronization with the second clock signal, and the second reset signal is generated based on the time point at which the first clock signal is generated; The second clock signal generated by latching the clock signal of
a reset signal generating means for outputting a logical sum with the reset signal of the first
and gate means that is set to an output state that outputs the data at the time of generation of the clock signal, and whose output state is reset based on the output from the reset signal generation means. circuit. (2) The reset signal generating means includes a D flip-flop whose data input terminal is supplied with the second clock signal and whose clock input terminal is supplied with the first clock signal; and the second clock signal. , and an OR gate that outputs a logical sum with the output from the D flip-flop.