JPS62182802A - Anti-fault process controller - Google Patents

Abstract

PURPOSE:To omit another control system consisting of plural processing means which function as spare ones in the same constitution and a data bus, by securing such a constitution where plural signal processing control means have all functions needed for each process control and the data buses of two systems are always used effectively. CONSTITUTION:In principle a control system works normally as long as one of the 1st-3rd signal processing control means 10-30 and one of the 1st and 2nd data buses DB1 and DB2 work normally. For instance, the 2nd control means 20 that is processing a function B is inapplicable owing to the occurrence of a fault or one of both control means 10 and 30 has a fault. Even under such conditions, the control system has the normal working as a whole. Furthermore this control system can have the satisfactorily normal working thanks to the functions of the 1st-3rd processing circuits CP1-CP3.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a failure handling process control device, and in particular,
The present invention relates to a fault response process control device suitable for various process control systems installed in plant aircraft, shipbuilding, etc.

[Conventional technology]

Plants, aircraft, shipbuilding, etc. are equipped with various control systems. In each of these fields, failures in control systems can directly lead to major accidents. For this reason, conventional control systems prepare in advance two or more control systems that function independently.
All of these are set to operational status. When a failure occurs, it is immediately detected and the control system is automatically switched, so that process control is executed without interruption.

[Problem that the invention seeks to solve]

However, in the conventional example described above, it is necessary to equip a control system consisting of a spare signal processing section, a data bus, a common storage section, etc. in a number corresponding to the failure response (backup) function. For this reason, the entire system becomes large-scale, and when the number of data buses increases, it takes up a lot of space and is time-consuming. On the other hand, although the backup system is in operation, it does not contribute to the process at all. For this reason, the system as a whole had the disadvantage that the efficiency of information processing and data transfer was extremely low compared to the size of the equipment.

[Purpose of the invention]

The present invention particularly improves the disadvantages of the conventional example, makes it possible to effectively back-amplify multiple control functions without deteriorating the process control function, and allows information to be reduced compared to the size of the equipment. The object is to provide a fault-responsive process control device that can significantly improve processing and data transfer efficiency.

[Means for solving problems]

The failure handling process control device according to the present invention has a plurality of signal processing control means for process control. These signal processing control means are connected in parallel by two data buses through which control signals and data signals can be passed simultaneously. Each of the signal processing control means normally executes a single function, and in the event of a failure, can substitute the signal processing function of other signal processing control means to simultaneously execute multiple functions, and the processing circuit A method is adopted in which the device is configured by a circuit and a storage circuit that stores each of the data signals and control signals processed by other processing circuits.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

The failure handling process control device shown in these figures includes first to third signal processing control means 10, 20 and 30,
The first and second parts are connected in parallel and connected to the controlled part.
It is composed of two systems of data buses DI31 and DB2.

The first signal processing control means 10 has a plurality of signal processing functions A
, B and C, and this processing circuit CP1 or other processing circuits CP2 and C20 to be described later.
It has a memory circuit MUI that stores signals processed by each of the two. The other second or third signal processing means 20 or 30 also includes a processing circuit CP2 or C20 that functions similarly,
They each have a memory circuit MU2 or MU3.

Each of the first to third storage circuits MUI to MU3 receives a control signal CS of all information common between each signal processing control means 10, 20 and 30, and a control signal CS of each of the first to third processing circuits CPI. ~Data signal D output from CP3
(A), D (B).

and D (C).

Also, the first to second data buses DBl and DB2
are the control signal C8 and the data signal D (A), respectively.
It has 11 forces that pass through D (C) and D (C) at the same time.

Each of the first to third processing circuits CPI to C20 has a pre-assigned function (A) during normal times.

One of B and C) is performed. The first and second data buses DBI and DB2 also receive the control signal CS or the data signals D(A) to D(C
) can be transferred separately to avoid duplication.

FIG. 1 shows the normal state. In the embodiment shown in FIG. 1, the first to third signal processing control means 10 to 30
Each of the processing circuits CPI to C20 is a first processing circuit C
The PI is assigned to process the ``F'' function, the second processing circuit CP2 is assigned to process the 8 functions, and the third processing circuit CP3 is assigned to process the C function. The control signal C8 communicated between each signal processing control means 10 to 30 is carried out via a data bus DBI as shown in FIG. Each signal processing control means 1
Data signal D between 0 and 30 (A) No LD (C
) is performed via the data bus DB2 in order to maintain continuity of process control during backup. These control signals CS and data signals D (A) to D (C) are transmitted to each signal processing control means IO.
The data is stored in common in the first to third memory circuit units M01 to MU3 installed in the memory circuits M01 to M30, respectively.

Next, a failure response operation when a failure occurs in the second signal processing control means 20 in the embodiment shown in FIG. 1 will be described. FIG. 2 shows the situation in this case, where there is no exchange of control signal cs and data signals D (A), D (B> and D (C)) in the second signal processing control means 20. I'm familiar with it.

As shown in FIG. 2, when the second signal processing control means 20, which was processing eight functions, becomes unusable due to the occurrence of a failure, the third processing circuit CP3 of the third signal processing control means 30 immediately The data signal D (B) for the B function stored in the memory circuit MU3 is read out and Bja function processing is performed. Therefore, the third processing circuit CP3 of the third signal processing control means 30 has the functions B and C, and processes them simultaneously.

In addition, as shown in FIG.
If the data bus DBI fails and becomes unavailable,
The receiver simultaneously communicates the data signals D (A) to D (C) and the control signal CS, and is configured to function so as to perform process control continuously.

In this embodiment, basically any one of the first to third signal processing control means 10 to 30 and one of the first and second data buses DBI and DB2 are normal. If so, the control system is configured to work normally, so in the case of Figure 2 above, and even in the case of Figure 1.
Or, even if either one of the third signal processing control means IO or 30 fails, the control system as a whole functions normally, and furthermore, the failures shown in FIGS. 2 and 3 occur simultaneously. However, this control system
The functions of PI to CP3 allow for sufficiently normal operation.

〔Effect of the invention〕

The failure-responsive process control device according to the present invention has the following effects because each of the plurality of signal processing control means has all the functions necessary for process control and always makes effective use of two data buses. Serve. (2) Unlike the conventional example, there is no need to provide another control system as a backup consisting of a plurality of processing means and data buses that are configured and function identically.

■A process control system that requires a backup function can be constructed with a control system consisting of a minimum number of processing means and a minimum system of data buses. ■During normal times, two systems of data buses are used effectively, so the information processing and transfer efficiency of the entire control system is significantly improved compared to the conventional example. (2) It is possible to provide an excellent fault-handling process control device that is fully equipped with fault-handling functions and is based on an unprecedented method.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a failure handling process control device according to the present invention, and FIGS. 2 and 3 are explanatory diagrams showing the operation of the embodiment shown in FIG. 1 when a failure occurs. 10...first signal processing control means, 2o...
. . . second signal processing control means, 30 . . . third
signal processing control means, CPI...first processing circuit, CR2...second processing circuit, CF2/old/
- Third processing circuit, MUI...first notation tα circuit, MU2...second storage circuit, MU3...
...Third storage circuit, DBI...First data bus, DB2...Second data bus, CS.
...Control signal, D (A) or D (C)...
...Data signal.

Claims (1)

[Claims] (1) A plurality of signal processing control means for process control are provided, and each of the signal processing control means is connected in parallel by two data buses capable of passing control signals and data signals simultaneously, and Each of the signal processing control means is provided with a processing circuit that normally performs a single function and, in the event of a failure, can substitute the signal processing function of the other signal processing control means and simultaneously execute multiple functions; What is claimed is: 1. A failure-responsive process control device comprising a circuit and a storage circuit that stores each of data signals and control signals processed by another processing circuit.